Test structures for secondary ion mass spectrometry analysis of patterned silicon wafers

Abstract

Secondary ion mass spectrometry (SIMS) analysis of patterned silicon wafers is complicated by the small areas available for study, the difficulty in finding the analysis location, the existence of thick insulating layers that cause charging, quantification of multilayer structures, and the presence of a high concentration of the element of interest adjacent to the area of study. Special SIMS test structures have been implemented to provide large, easily identifiable, analysis areas that have proved to be an asset in both process characterization and failure analysis of product wafers. Descriptions are provided for test structures ranging from a 400×600-μm pattern in a test chip design to a 100×125-μm pattern on a product wafer. Applications are shown for test sites generated by projection and step and repeat printing. The grid region between devices provides a practical location for SIMS test areas on current product wafers. The amount of grid space available may be insufficient to accommodate the full complement of structures needed to characterize a particular process technology, but space requirements can be reduced by the use of smaller patterns for certain applications. Analysis of patterned wafers using grid test patterns can still be affected by charging, and often requires the removal of insulating layers by etching and the use of primary beams that are well focused and do not impact on the sample outside of the test pattern.