Test Structure for Process and Product Evaluation

Rigaud, F.; Portal, J.M.; Aziza, Hassen; Nee, D.; Vast, J.; Auricchio, C.; Borot, B.

doi:10.1109/icmts.2007.374471

Cited by 5 publications

(1 citation statement)

References 2 publications

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“…In [8], parametric test structures are placed in scribe-lines (i.e. empty space between dies) to detect process variations for circuit performance evaluation without sacrificing wafer area.…”

Section: Introductionmentioning

confidence: 99%

Design dependent process monitoring for back-end manufacturing cost reduction

Chan¹,

Pant²,

Cheng³

et al. 2010

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Abstract-Short-loop process monitoring structures (usually simple device I − V , C − V measurements made after M1 fabrication) are commonly put in wafer scribe-lines. These test structures are almost always design independent and measured/monitored by the foundry to keep track of process deviations. We propose a design-dependent process monitoring strategy which can accurately predict design performance based on simple I ef f -based delay and I of f -based leakage power estimates. We show that our strategy works much better (0.99 correlation vs. 0.87) compared to conventional designindependent monitors. Further, we use the predicted delay and leakage power for early yield estimation for pruning bad wafers to save test and back-end manufacturing costs We show that wafer pruning based on our approach can achieve upto 98% of the maximum achievable benefit/profit. We design the measurement and prediction schemes so as to minimize data as well as computation that needs to be kept track of during wafer fabrication. Such design-dependent process monitoring can help target process control/optimization effort, enable quicker yield ramp besides saving test and manufacturing costs.

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Section: Introductionmentioning

confidence: 99%