Test Strategies for Reliable Runtime Reconfigurable Architectures

Bauer, Lars; Braun, Claus; Imhof, Michael E.; Kochte, Michael A.; Schneider, Eric; Zhang, Hongyan; Henkel, Jörg; Wunderlich, Hans-Joachim

doi:10.1109/tc.2013.53

Cited by 27 publications

(22 citation statements)

References 47 publications

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“…Nevertheless, the significant voltage scaling and the dramatic increase of the number of transistors make TID again significant in modern space electronics [20]. To the best of our knowledge, the only work addressing the problem of detecting faults induced in FPGA devices by the long-term exposure to radiation is the one reported in [21]. This work focuses on the architecture used for testing reconfigurable areas inside an FPGA device, i.e., the Configurable Logic Blocks (CLBs) and on the scheduling of the test activities.…”

Section: Related Workmentioning

confidence: 99%

OLT(RE)²: An On-Line On-Demand Testing Approach for Permanent Radiation Effects in Reconfigurable Systems

Cozzi

Korf

Cassano

et al. 2018

IEEE Trans. Emerg. Topics Comput.

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Reconfigurable systems gained great interest in a wide range of application fields, including aerospace, where electronic devices are exposed to a very harsh working environment. Commercial SRAM-based FPGA devices represent an extremely interesting hardware platform for this kind of systems since they combine low cost with the possibility to utilize state-of-the-art processing power as well as the flexibility of reconfigurable hardware. In this paper we present OLT(RE)2: an on-line on-demand approach to test permanent faults induced by radiation in reconfigurable systems used in space missions. The proposed approach relies on a test circuit and on custom place-and-route algorithms. OLT(RE)2 exploits partial dynamic reconfigurability offered by todayâ€™s SRAM-based FPGAs to place the test circuits at run-time. The goal of OLT(RE)2 is to test unprogrammed areas of the FPGA before using them, thus preventing functional modules of the reconfigurable system to be placed on areas with faulty resources. Experimental results have shown that (i) it is possible to generate, place and route the test circuits needed to detect on average more than 99 % of the physical wires and on average about 97 % of the programmable interconnection points of an arbitrary large region of the FPGA in a reasonable time and that (ii) it is possible to download and run the whole test suite on the target device without interfering with the normal functioning of the system

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Section: Related Workmentioning

confidence: 99%

OLT(RE)²: An On-Line On-Demand Testing Approach for Permanent Radiation Effects in Reconfigurable Systems

Cozzi

Korf

Cassano

et al. 2018

IEEE Trans. Emerg. Topics Comput.

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“…Two online test methods are combined to achieve reliable reconfiguration and high system dependability [15].…”

Section: Proactive Online Testsmentioning

confidence: 99%

“…After the configuration, PORT is applied periodically to test for faults in the ConBrought to you by | New York University Bobst Library Technical Services Authenticated Download Date | 6/24/15 11:52 AM tainer interfaces and errors in its configuration bits that might have occurred after the configuration process. Periodic application of PRET and PORT by the runtime system provides different user-selectable trade-offs between fault detection latency and performance impact [15]. For instance, at a desired test latency of 3.8 seconds, only a marginal performance impact of at most 4.4% is induced.…”

Section: Proactive Online Testsmentioning

confidence: 99%

“…This work is part of the DFG funded priority program SPP 1500 "Dependable Embedded Systems"¹. The paper covers three projects related to system-and hardwarearchitecture, namely VirTherm-3D (system-level task mapping and communication) [12][13][14], OTERA (FGRP) [15][16][17], and ARES (CGRA) [18][19][20][21]. It is part of the IT special issue on "Embedded Systems".…”

Section: Introductionmentioning

confidence: 99%

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Adaptive multi-layer techniques for increased system dependability

Bauer

Henkel

Herkersdorf

et al. 2015

It - Information Technology

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Achieving system-level dependability is a demanding task. The manifold requirements and dependability threats can no longer be statically addressed at individual abstraction layers. Instead, all components of future multi-processor systems-on-chip (MPSoCs) have to contribute to this common goal in an adaptive manner. In this paper we target a generic heterogeneous MPSoC that combines general purpose processors along with dedicated application-specific hard-wired accelerators, finegrained reconfigurable processors, and coarse-grained reconfigurable architectures. We present different reactive and proactive measures at the layers of the runtime system (online resource management), system architecture (global communication), micro architecture (individual tiles), and gate netlist (tile-internal circuits) to address dependability threats.

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“…1) In particular, dynamically reconfigurable logic platform is expected to serve as a new computing paradigm. [2][3][4][5][6] A multi-context field-programmable gate array (MC-FPGA) in which configuration data are instantaneously switched on demands is a viable candidate for implementing dynamically reconfigurable logic platforms. [7][8][9] By utilizing the MC-FPGA, multiple logic functions are integrated in a single chip, we can also virtualize a large-scale system in limited hardware resource.…”

Section: Introductionmentioning

confidence: 99%

Nonvolatile field-programmable gate array using 2-transistor–1-MTJ-cell-based multi-context array for power and area efficient dynamically reconfigurable logic

Suzuki

Hanyu

2015

Jpn. J. Appl. Phys.

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A dynamically reconfigurable nonvolatile field-programmable gate array (FPGA) with a multi-context (MC) cell array structure that uses threeterminal magnetic tunnel junction (MTJ) devices is proposed. The use of single-ended circuitry together with a 2-transistor and 1-MTJ (2T-1MTJ) context cell allows for the minimization of the area overhead of the context array with nonvolatile storage capability. As the 2T-1MTJ cell has no power line, the leakage current overhead is also minimized. With the proposed implementation, the transistor counts and leakage power during power-on are reduced by 59 and 71%, respectively, compared to the static random-access memory (SRAM)-based implementation using 40-nm CMOS technology.

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Test Strategies for Reliable Runtime Reconfigurable Architectures

Cited by 27 publications

References 47 publications

OLT(RE)²: An On-Line On-Demand Testing Approach for Permanent Radiation Effects in Reconfigurable Systems

OLT(RE)²: An On-Line On-Demand Testing Approach for Permanent Radiation Effects in Reconfigurable Systems

Adaptive multi-layer techniques for increased system dependability

Nonvolatile field-programmable gate array using 2-transistor–1-MTJ-cell-based multi-context array for power and area efficient dynamically reconfigurable logic

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Test Strategies for Reliable Runtime Reconfigurable Architectures

Cited by 27 publications

References 47 publications

OLT(RE)2: An On-Line On-Demand Testing Approach for Permanent Radiation Effects in Reconfigurable Systems

OLT(RE)2: An On-Line On-Demand Testing Approach for Permanent Radiation Effects in Reconfigurable Systems

Adaptive multi-layer techniques for increased system dependability

Nonvolatile field-programmable gate array using 2-transistor–1-MTJ-cell-based multi-context array for power and area efficient dynamically reconfigurable logic

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Product

Resources

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OLT(RE)²: An On-Line On-Demand Testing Approach for Permanent Radiation Effects in Reconfigurable Systems

OLT(RE)²: An On-Line On-Demand Testing Approach for Permanent Radiation Effects in Reconfigurable Systems