Test Program Generation for Functional Verification of PowePC Processors in IBM

Abstract-Throughout its history, from the early four-circuit gate-array chips of the late 1960s to today's billion-transistor multichip module, IBM has invested in tools to support its leading-edge technology and high-performance product development. The combination of demanding designs and close cooperation among product, technology, and tool development has given rise to many innovations in the electronic design automation (EDA) area and provided IBM with a significant competitive advantage. This paper highlights IBM's contributions over the last four decades and presents a view of the future, where the best methods of multimillion gate ASIC and gigahertz microprocessor design are converged to enable highly productive system-on-a-chip designs that include widely diverse hardware and software components.

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Functional vector generation for HDL models using linear programming and Boolean satisfiability

Fallah

Devadas

Keutzer

2001

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Our strategy for automatic generation of functional vectors is based on exercising selected paths in the given hardware description language (HDL) model. The HDL model describes interconnections of arithmetic, logic and memory modules. Given a path in the HDL model, the search for input stimuli that exercise the path can be converted into a standard satis ability checking problem by expanding the arithmetic modules into logic-gates. However, this approach is not very e cient. We present a new HDL-satis ability checking algorithm that works directly on the HDL model. The primary feature of our algorithm is a seamless integration of linearprogramming techniques for feasibility checking of arithmetic equations that govern the behavior of data-path modules, and satis ability checking for logic equations that govern the behavior of control modules. This feature is critically important to e ciency, since it avoids module expansion and allows us to work with logic and arithmetic equations whose cardinality tracks the size of the HDL model. We describe the details of the HDL-satis ability checking algorithm in this paper. Experimental results which show signi cant speedups over state-of-the-art gate-level satis ability checking methods are included.

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Test Program Generation for Functional Verification of PowePC Processors in IBM

Cited by 49 publications

References 4 publications

Solving the generalized mask constraint for test generation of binary floating point add operation

Solving the generalized mask constraint for test generation of binary floating point add operation

EDA in IBM: past, present, and future

Functional vector generation for HDL models using linear programming and Boolean satisfiability

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