Test Pattern Generation and Critical Path Selection in the Presence of Statistical Delays

Javvaji, Pavan Kumar; Tragoudas, Spyros

doi:10.1109/tvlsi.2019.2941426

Cited by 3 publications

(1 citation statement)

References 16 publications

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“…Path selection, where a subset of the path delay faults are targeted, is necessary because of the large number of paths a circuit can have. Path selection criteria focus on the longest paths [3], or the longest path through every line [2], considering the technology and process variations as in [20], [21], [23], [29], [33], [34], [35] and [36]; the testability of the paths as in [3], [5], [8] and [9]; the operating conditions [10]; or the advantage of maintaining functional operation conditions as in [15] and [31].…”

Section: Introductionmentioning

confidence: 99%

Longest Path Selection Based on Path Identifiers

Pomeranz

2024

IEEE Access

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A small delay defect adds a small extra delay to the propagation time of a signal through a gate or line. Small delay defects can occur during fabrication or during the lifetime of a chip. When a path with small delay defects has a delay that exceeds its permissible value based on the clock period, timing failures may occur. To detect small delay defects, test generation procedures target path delay faults that are associated with the longest paths. Storage of paths can have a significant memory overhead. To avoid this overhead, it was shown earlier that paths can be associated with unique integer identifiers. The identifiers are based on a labeling of the circuit lines with two integer labels that are computed in linear time. This article suggests a third integer label, also computed in linear time, that allows the longest paths to be identified based only on their integer identifiers. The third label ensures that the longest path has identifier 0, and shorter paths have larger identifiers. Thus, with an exception discussed and addressed in the article, it is possible to target the longest paths for test generation by targeting the paths with identifiers 0, 1, 2, .... An identifier needs to be translated into a physical path only when it is targeted for test generation. The article applies the new labeling to benchmark circuits and presents experimental results to demonstrate its effectiveness.INDEX TERMS Launch-on-capture tests, launch-on-shift tests, path delay faults, path selection, test generation.

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Section: Introductionmentioning

confidence: 99%

Longest Path Selection Based on Path Identifiers

Pomeranz

2024

IEEE Access

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Path Unselection for Path Delay Fault Test Generation

Pomeranz

2023

IEEE Trans. VLSI Syst.

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Towards an Automatic Test Generation Method for Systems of Systems Based on Fault Injection and Model-Based Systems Engineering

Tian

Jing

2022

Applied Sciences

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The emergence and development of systems of systems (SoSs) have expanded the complexity and adaptability of systems engineering. Due to the heterogeneity of its constituent systems, designing and analyzing an SoS faces enormous challenges. Therefore, the verification of an SoS is important in its design phase. However, related methods and techniques are still in the preliminary research state, mainly for requirements verification and system verification, and a lack of efforts in design verification for SoSs. Aiming to provide the ability to detect hazardous states at the design phase, we worked on a novel method for automatically generating test cases for model verification in SoSs. Considering the characteristics of SoSs, the method adopts fault injection and model-based system engineering as the foundations to extend the automated generation capability of test cases. This paper proposes an automatic test generation (ATG) method for an SoS based on fault injection and model-based systems engineering (MBSE). It is meant to generate test cases that can be used to check the effectiveness of fault detection or identification in SoSs and for the effective testing of their constituent systems (CSs). This paper discusses scenario generation and ATG in linear temporal logic and designs an algorithm to generate traces as test suites, taking into account the constraints of the models. By establishing a concept alignment example (CAE) as the experimental use case, three test scenarios are generated automatically, showing that the use of the proposed ATG method provides a reasonable hazardous detection capability for verification in SoS design. The main contributions of the paper are (1) the description of the proposed two-phase ATG approach with fault-centric modeling activities and generation-related activities; (2) the explanation of the designed ATG algorithm at both high and low levels; and (3) the discussion of the experiment in an emergency response CAE with three generated test scenarios.

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Test Pattern Generation and Critical Path Selection in the Presence of Statistical Delays

Cited by 3 publications

References 16 publications

Longest Path Selection Based on Path Identifiers

Longest Path Selection Based on Path Identifiers

Path Unselection for Path Delay Fault Test Generation

Towards an Automatic Test Generation Method for Systems of Systems Based on Fault Injection and Model-Based Systems Engineering

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