Test methodology for freescale's high performance e600 core based on powerPC instruction set architecture

Tendolkar, N.; Belete, D.; Razdan, A.; Reyes, Heelinn Ivania Calero; Schwarz, Bill; Sullivan, M.

doi:10.1109/test.2005.1583968

Cited by 11 publications

(4 citation statements)

References 11 publications

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“…In [10], the testability features of an ARM microprocessor core are presented that include SF patterns, TF patterns and path delay patterns. More recently, in [12], the authors describe the test methodology for Freescale's e600 core. The methodology includes at-speed logic BIST, scan-based delay test and memory BIST.…”

Section: Prior Workmentioning

confidence: 99%

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An Integrated Framework for At-Speed and ATE-Driven Delay Test of Contract-Manufactured ASICs

Iyengar

Pichamuthu²,

Ferko³

et al. 2007

25th IEEE VLSI Test Symposium (VTS'07)

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In contract manufacturing, the circuit netlist is owned by the ASIC customer. The manufacturer is required to work strictly within the design structure established by the customer. To manufacture high-quality components in this environment, it is critical to meet the customer's mandated quality and performance criteria, while minimizing hardware overhead and introducing litle or no design change. In this paper, we present a test framework for contract-manufactured ASICs using lowcost testers. Key aspects of the framework are low hardware overhead, significant savings in test data volume and test cost, and tight integration of the at-speed and ATE-driven test components to the design and manufacturing process.

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Section: Prior Workmentioning

confidence: 99%

“…At-speed test based on automatic test pattern generation (ATPG) has become a popular approach to apply structural test patterns at functional speeds [10,12]. However, many existing methods are applicable to only a few circuit types, or require detailed knowledge of the circuit functionality.…”

Section: Introductionmentioning

confidence: 99%

An Integrated Framework for At-Speed and ATE-Driven Delay Test of Contract-Manufactured ASICs

Iyengar

Pichamuthu²,

Ferko³

et al. 2007

25th IEEE VLSI Test Symposium (VTS'07)

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show abstract

“…In [10], methods for at-speed deterministic test are reported. In [3], the authors describe at-speed test for Freescale's e600 core. In [2], an ASST methodology for contract manufactured ASICs is presented.…”

Section: Prior Workmentioning

confidence: 99%

“…At-speed test has become a popular low-cost approach to detect subtle delay failures in manufacturing [2], [3]. However, at-speed test for catastrophic defects does not address the problem of delays caused by process variation [4].…”

Section: Introductionmentioning

confidence: 99%

Variation-aware performance verification using at-speed structural test and statistical timing

Iyengar¹,

Xiong²,

Venkatesan³

et al. 2007

2007 IEEE/ACM International Conference on Computer-Aided Design

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Meeting the tight performance specifications mandated by the customer is critical for contract manufactured ASICs. To address this, at speed test has been employed to detect subtle delay failures in manufacturing. However, the increasing process spread in advanced nanometer ASICs poses considerable challenges to predicting hardware performance from timing models. Performance verification in the presence of process variation is difficult because the critical path is no longer unique. Different paths become frequency limiting in different process corners. In this paper, we present a novel variation-aware method based on statistical timing to select critical paths for structural test. Node criticalities are computed to determine the probabilities of different circuit nodes being on the critical path across process variation. Moreover, path delays are projected into different process corners using their linear delay function forms. Experimental results for three multimillion gate ASICs demonstrate the effectiveness of our methods.

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Built-in generation of multi-cycle broadside tests

Pomeranz¹

2012

2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

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Test methodology for freescale's high performance e600 core based on powerPC instruction set architecture

Cited by 11 publications

References 11 publications

An Integrated Framework for At-Speed and ATE-Driven Delay Test of Contract-Manufactured ASICs

An Integrated Framework for At-Speed and ATE-Driven Delay Test of Contract-Manufactured ASICs

Variation-aware performance verification using at-speed structural test and statistical timing

Built-in generation of multi-cycle broadside tests

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