Test generation using SAT-based bounded model checking for validation of pipelined processors

Koo, Heon-Mo; Mishra, Prabhat

doi:10.1145/1127908.1127991

Cited by 26 publications

(10 citation statements)

References 9 publications

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“…Moreover, the framework has been constructed specifically to complement modern engineering practice: allowing direct use of the HDL and assembly language, and utilizing IEEE PSL coverage goals. This ability to fit in with modern design flow is one of the key advantages of our framework over other formally-based testing methods for microprocessors [18,12,13]. Another key advantage over other formally-based testing methods is that our framework does not require monolithic use of model checking algorithms, which have well known scalability problems in terms of symbolically representing large systems.…”

Section: Discussionmentioning

confidence: 99%

“…The Ph.D. thesis of Mishra [18] describes how to use standard BDD-based model checkers and an abstract model of the microprocessor to automatically generate test programs. In subsequent work [12,13], Koo and Mishra have expanded on these techniques, adding a method of model decomposition and also utilizing bounded model checking. Another method where model checking is used as part of a program generation scheme is given in [23].…”

Section: Introductionmentioning

confidence: 99%

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Directed-Logical Testing for Functional Verification of Microprocessors

Katelman

Meseguer

Escobar

2008

2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design

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The length of the microprocessor development cycle is largely determined by functional verification, where contemporary practice relies primarily on constraint-based random stimulus generation to drive a simulation-based methodology. However, formal methods are, in particular, gaining wider adoption and are seen as having potential to bridge large gaps left by current techniques. And many gaps still remain. In this paper we propose directedlogical testing: a new method of stimulus generation based on purely logical techniques (i.e. formal methods). As far as we know, our methodology represents the first endto-end mathematical formalization of the stimulus generation problem. Therefore, a major contribution of this paper is the definition of a class of logical propositions that relate the actual microprocessor implementation, the assembly program stimulus, and a coverage goal. These propositions are given in rewriting logic, and use the idea of rewriting semantics to automatically formalize within a common logical framework the microprocessor implementation and assembly programs. To solve these propositions, we demonstrate how narrowing and user-defined narrowing strategies can be used as a scalable logical framework. In addition, we describe two classes of effective strategies that can be used for many microprocessors and common coverage goals. Finally, we describe a prototype tool implementation and present empirical data to demonstrate the feasibility of our methodology. Since narrowing and user-defined narrowing strategies within rewriting logic do not yet have tool support, our prototype tool uses standard rewriting and user-defined rewriting strategies to simulate narrowing.

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Section: Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Directed-Logical Testing for Functional Verification of Microprocessors

Katelman

Meseguer

Escobar

2008

2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design

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“…Algorithm 2 describes the widely used test generation procedure using BMC [27,28]. This algorithm takes the model M generated from a design model and properties as inputs and generates test suite extracted from the counterexamples.…”

Section: Test Generation Algorithmmentioning

confidence: 99%

Automated Generation of Directed Tests

Chen

Qin

Koo

et al. 2012

System-Level Validation

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Increasing complexity combined with decreasing time-to-market requirement make the functional validation a major bottleneck in the HW/SW design flow. As a most widely used validation method, simulation employs tests in the following three categories: random, constrained-random tests, and directed tests. Random and constrained-random testing [1] are easy to implement; nevertheless, it is hard to guarantee the convergence to the testing target (i.e., functional coverage). In contrast, directed testing [2] uses fewer tests to obtain the required functional coverage since it exploits the design structure information. By applying the directed tests, the validation effort can be drastically reduced. However, most directed test generation methods assume the expert knowledge of the design under validation (DUV). Due to the inevitable human intervention, current directed test generation methods are laborious and error-prone. Therefore, it is necessary to develop efficient techniques to automate the process of directed test generation.Model checking [3] is a formal method which can verify whether a temporal property is satisfied for a finite state concurrent system. In model checking, a design is modeled as a state transition graph, called a Kripke structure [3], which is a fourtuple model M = (S, S 0 , R, L). S is a finite set of states. S 0 is a set of initial states, where S 0 ⊆ S. R : S → S is a transition relation between states, where for every state s ∈ S, there is a state s ∈ S such that the state transition (s, s ) ∈ R. L : S → 2 AP is the labeling function to mark each state with a set of atomic propositions (AP) that hold in that state. Properties are expressed as linear temporal logic (LTL) and computational tree logic (CTL) formulas to describe expected design behaviors. For a formal model M of the design and a property p, the model checking is to find whether all states in S satisfy p or not. If there does not exist a reachable error state from initial states, the design satisfies the property, i.e., M |= p. Otherwise, the property does not hold for the design, and a variable assignment trace (counterexample) from an initial state to the error state will be reported. Such a trace can be used as a test to activate the scenario described by the negation of the checked property p.M. Chen et al., System-Level Validation,

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“…Incremental SAT solvers [25][26][27] tried to mitigate the impact of choosing an incorrect initial bound by exploiting similarity and forwarding conflict clauses, but it is disadvantageous for deep counterexamples due to accumulation of iterative running time. A method to determine the bound for each test generation scenario has been developed in [28,29], thereby making SAT-based BMC useful for directed test generation in pipelined processors.…”

Section: Related Workmentioning

confidence: 99%