Test generation through logic programming

Svanæs, Dag; Einar, J.

doi:10.1016/0167-9260(84)90006-3

Cited by 14 publications

(5 citation statements)

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“…The same circuit description can be used in various applications including simulation, formal verification and fault diagnosis (see [62]). Similar ways of describing hardware in logic programming are reported in [11,22,32,33,68].…”

Section: Circuit Descriptionmentioning

confidence: 74%

Constraint satisfaction using constraint logic programming

Hentenryck

Simonis

Dincbas

1992

Artificial Intelligence

316

312

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Van Hentenryck, P., H. Simonis and M. Dincbas, Constraint satisfaction using constraint logic programming, Artificial Intelligence 58 (1992) 113-159.Constraint logic programming (CLP) is a new class of declarative programming languages whose primitive operations are based on constraints (e.g. constraint solving and constraint entailment). CLP languages naturally combine constraint propagation with nondeterministic choices. As a consequence, they are particularly appropriate for solving a variety of combinatorial search problems, using the global search paradigm, with short development time and efficiency comparable to procedural tools based on the same approach. In this paper, we describe how the CLP language cc(FD), a successor of CHIP using consistency techniques over finite domains, can be used to solve two practical applications: test-pattern generation and car sequencing. For both applications, we present the cc(FD) program, describe how constraint solving is performed, report experimental results, and compare the approach with existing tools.

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Section: Circuit Descriptionmentioning

confidence: 74%

Constraint satisfaction using constraint logic programming

Hentenryck

Simonis

Dincbas

1992

Artificial Intelligence

316

312

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“…CHN89 [40] in Table 3. 6 In comparison, the single greedy strategy G1 with a backtrack limit of 15 fails to complete on only 105 redundant faults for the same seven networks.…”

Section: Efficiencymentioning

confidence: 97%

“…Most test generation algorithms use analysis of a network (or equation) to determine a variable ordering, such as the backtracing heuristics in a structural algorithm. The orderings used by early SAT-based algorithms depend primarily on the underlying solvers, although they can be influenced by ordering the problem description [6] or the use of other mechanisms [13]. Recent SATbased algorithms [14,15,22,16,23,17] analyze the 2-clauses of an equation, satisfying the easy part of the equation and then checking if the assignment also satisfies the entire equation.…”

Section: Greedy Searchmentioning

confidence: 99%

“…For ABR92 [45], it is not clear if all redundancies are successfully removed, and algorithm MEN94 [35] fails to remove 298 redundant faults. 6…”

Section: Robustnessmentioning

confidence: 99%

“…Most nonstructural algorithms use a reduction to SAT or its dual, referred to collectively as SAT-based algorithms, because the reduction is straightforward, SAT is a fundamental problem which has been widely studied, and the formulation as a set of characteristic functions directly fits the paradigm of logic programming. The overall approach of existing SAT-based algorithms [5,6,7,8,9,10,11,12,13,14,15,16,17] is to translate the D-algorithm problem formulation into a characteristic equation (in product-of-sums form for SAT, or sum-of-products form for the dual), and then solve the equation using a branch-andbound search.…”

Section: Introductionmentioning

confidence: 99%

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Combinational test generation using satisfiability

Stephan

Brayton

Sangiovanni-Vincentelli

1996

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

246

165

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We present a robust and efficient algorithm for combinational test generation using a reduction to satisfiability (SAT). The algorithm, TEGUS, has the following features. We choose a form for the test set characteristic equation which minimizes its size. The simplified equation is solved by an algorithm for SAT using simple, but powerful, greedy heuristics, ordering the variables using depth-first search and selecting a variable from the next unsatisfied clause at each branching point. For difficult faults the computation of global implications is iterated, which finds more implications than previous approaches and subsumes structural heuristics such as unique sensitization. Without random tests or fault simulation, TEGUS completes on every fault in the ISCAS networks, demonstrating its robustness, and is 11 times faster for those networks which have been completed by previous algorithms. Our publicly available implementation of TEGUS can be used as a base line for comparing test generation algorithms; we present comparisons with 45 recently published algorithms. TEGUS combines the advantages of the elegant organization of SAT-based algorithms, such as that by Svanaes, with the efficiency of structural algorithms, such as the D-algorithm.

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Application of constraint logic programming for VLSI CAD tools

Beckmann

Bieker

Markhof

Constraints in Computational Logics

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This paper describes the application of CLP (constraint logic programming) to several digital circuit design problems. It is shown that logic programming together with efficient constraint propagation techniques is an adequate programming environment for complex real world problems like high level synthesis, simulation, code generation, and memory synthesis. Different types of constraints -Boolean, integer, symbolic, structural, and type binding ones -are used to express relations between the components of a digital circuit and efficient propagation is achieved by the coroutining mechanism. To deal with the increasing complexity of digital circuits we use HDL's (hardware description languages) to represent structure and behaviour of circuits. I IssuesThis paper describes the successful use of logic programming extended by constraints to solve complex real world problems in the area of digital circuit design: high level synthesis, simulation, code generation, and memory synthesis. Instead of other systems in this area ours are able to work on a high level of abstraction and to deal with hardware description languages (HDLs). II ResultsIt has been shown that logic programming extended by constraints is an adequate mechanism to solve problems in the area of digital circuit design. Working systems for synthesis, simulation, test, code generation, and memory synthesis have been implemented in ECLIPSE [5]. Boolean, linear, structural, and type binding constraints are used to restrict the design space. So unneccessary backtracking as performed in PROLOG could be avoided. Using the combination of logic computation and constraints leads to new concepts to solve these kinds of problems. Some examples of effective constraints are given. Results are considered in the context of runtime, length of code, and design space restriction. III Significance and Relevance to the ConferenceAn important aspect for developing a new programming paradigm is to demonstrate its advantages and disadvantages. The only possibility to do this is by studying applications of the paradigm. Preferred application areas for the new style have to be found and tested to close the gap between the theoretical framework and potential applications.So this paper describes practical applications of combining computational logics and constraints. Several types of constraints -Boolean, linear, structural and type binding constraints -are used to develop working systems for complex real world problems in the area of digital circuit design. It is shown that the combination of logic programming and constraints gets practical relevance even for large software products.

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Test generation through logic programming

Cited by 14 publications

References 1 publication

Constraint satisfaction using constraint logic programming

Constraint satisfaction using constraint logic programming

Combinational test generation using satisfiability

Application of constraint logic programming for VLSI CAD tools

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