Test generation for Gigahertz processors using an automatic functional constraint extractor

Tupuri, R.S.; Krishnamachary, Arun; Abraham, Jacob A.

doi:10.1145/309847.310018

Cited by 31 publications

(2 citation statements)

References 6 publications

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“…Previously, Tupuri et al and Vishakantaiah et al have proposed a methodology to systematically extract structural con- straints for components of a processor from the processor description in hardware description language (HDL) [26]- [28]. However, it should be noted that not all architectural constraints can be extracted from structural descriptions [29].…”

Section: )mentioning

confidence: 99%

Software-based self-testing methodology for processor cores

Chen

Dey

2001

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

187

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At-speed testing of gigahertz processors using external testers may not be technically and economically feasible. Hence, there is an emerging need for low-cost high-quality self-test methodologies that can be used by processors to test themselves at-speed. Currently, built-in self-test (BIST) is the primary self-test methodology available. While memory BIST is commonly used for testing embedded memory cores, complex logic designs such as microprocessors are rarely tested with logic BIST. In this paper, we first analyze the issues associated with current hardware-based logic-BIST methodologies by applying a commercial logic-BIST tool to two processor cores. We then propose a new software-based self-testing methodology for processors, which uses a software tester embedded in the processor memory as a vehicle for applying structural tests. The software tester consists of programs for test generation and test application. Prior to the test, structural tests are prepared for processor components in the form of self-test signatures. During the process of self-test, the test generation program expands the self-test signatures into test sets and the test application program applies the tests to the components under test at the speed of the processor. Application of the novel software-based self-test method demonstrates its significant cost/fault coverage benefits and its ability to apply at-speed test while alleviating the need for high-speed testers.

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Section: )mentioning

confidence: 99%

Software-based self-testing methodology for processor cores

Chen

Dey

2001

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

187

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“…For a large processor, it is virtually impossible to extract module-level constraints manually. Automated constraint extraction methods have been proposed in [12] [13], in which constraints imposed by the hardware environment surrounding a module can be extracted from the RTL description. However, structural constraints cannot be directly used in SBST, as they are only a subset of instructionimposed functional constraints.…”

Section: Introductionmentioning

confidence: 99%

A scalable software-based self-test methodology for programmable processors

Chen

Ravi²,

Raghunathan³

et al. 2003

Proceedings of the 40th Annual Design Automation Conference

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Software-based self-test (SBST) is an emerging approach to address the challenges of high-quality, at-speed test for complex programmable processors and systems-on chips (SoCs) that contain them. While early work on SBST has proposed several promising ideas, many challenges remain in applying SBST to realistic embedded processors. We propose a systematic scalable methodology for SBST that automates several key steps. The proposed methodology consists of (i) identifying test program templates that are well suited for test delivery to each module within the processor, (ii) extracting input/output mapping functions that capture the controllability/observability constraints imposed by a test program template for a specific module-under-test, (iii) generating module-level tests by representing the input/output mapping functions as virtual constraint circuits, and (iv) automatic synthesis of a software selftest program from the module-level tests. We propose novel RTL simulation-based techniques for template ranking and selection, and techniques based on the theory of statistical regression for extraction of input/output mapping functions. An important advantage of the proposed techniques is their scalability, which is necessitated by the significant and growing complexity of embedded processors.To demonstrate the utility of the proposed methodology, we have applied it to a commercial state-of-the-art embedded processor (Xtensa™ from Tensilica Inc.). We believe this is the first practical demonstration of software-based self-test on a processor of such complexity. Experimental results demonstrate that software self-test programs generated using the proposed methodology are able to detect most (95.2%) of the functionally testable faults, and achieve significant simultaneous improvements in fault coverage and test length compared with conventional functional test.

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A novel RTL behavioral description based ATPG method

Yin

Min

et al. 2003

J. Comput. Sci. & Technol.

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Test generation for Gigahertz processors using an automatic functional constraint extractor

Cited by 31 publications

References 6 publications

Software-based self-testing methodology for processor cores

Software-based self-testing methodology for processor cores

A scalable software-based self-test methodology for programmable processors

A novel RTL behavioral description based ATPG method

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