Test cost minimization for hybrid BIST

A hybrid BIST architecture and its optimization for SoC testing

“…In our approach we use a fast estimation method proposed in [13] to find an initial solution. This estimation method is based on number of not yet covered faults R NOT (i) and can be obtained from the pseudorandom test simulation results (Table 1).…”

“…The pseudorandom test vectors can be generated either by hardware or by software and later complemented by the stored deterministic test set which is specially designed to shorten the pseudorandom test cycle and to target the random resistant faults. The basic idea of Hybrid BIST was discussed in [13].…”

Hybrid BIST Test Scheduling Based on Defect Probabilities

“…Therefore different hybrid approaches have been proposed, where pseudorandom test patterns are complemented with deterministic test patterns, which are applied from the ATE or, in special situations, from the onchip memory. These approaches are generally referred to as hybrid BIST [3,4]. Such a hybrid approach reduces the memory requirements compared to the pure deterministic testing, while providing higher fault coverage and reduced test times compared to the stand-alone BIST solution.…”

Hybrid BIST time minimization for core-based systems with STUMPS architecture

“…One solution to the problem is to complement pseudorandom test patterns with deterministic test patterns, applied from the on-chip memory or, in special situations, from the ATE. This approach is usually referred to as hybrid BIST [3].…”

“…Our earlier work, [3], [12] and [13], has been concentrating on test cost calculation and hybrid BIST optimization for single-core designs. Recently we have proposed a methodology for test time minimization, under memory constraints, for multi-core systems, where only combinatorial cores were assumed [14].…”