Proceedings of the 2005 International Conference on Microelectronic Test Structures, 2005. ICMTS 2005.
DOI: 10.1109/icmts.2005.1452281
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Test chip for inductance characterization and modeling for sub-100nm X architecture and Manhattan chip design

N.D. Arora
1
,
Li Song
2
,
S. Shah
3
et al.
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