Test Access Mechanism for Multiple Identical Cores

Giles, G.; Wang, Jing; Sehgal, Anuja; Balakrishnan, K.J.; Wingfield, J.

doi:10.1109/test.2008.4700553

Cited by 36 publications

(20 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In [12], a test access mechanism, which supports three test modes for multiple identical cores, the fullrate self-compare mode, the interleaved self-compare mode and inter-core compare mode, is described. Although it is flexible and scalable, pattern transformation and issuing proper TAM instructions is complex, and the support for X-masking will cost extra test time.…”

Section: Data-synchronous-comparator (Dsc) For Identical Coresmentioning

confidence: 99%

“…Unlike [12], we use balance registers to achieve straightforward on-chip comparisons. As shown in Fig.7, there are four stages of scan input balance registers (SIBR) and zero stage of scan output balance registers (SOBR) for core 0 , and three stages of SIBRs and one stage of SOBR for core 1 , and so forth.…”

Section: Data-synchronous-comparator (Dsc) For Identical Coresmentioning

confidence: 99%

“…They receive the same stimulus at the same cycle and enter the capture procedure simultaneously. Therefore commands which control the specific operations in [12] are not needed any more. In addition, test patterns of testing one core separately are the same with that of testing all the cores concurrently.…”

Section: Data-synchronous-comparator (Dsc) For Identical Coresmentioning

confidence: 99%

“…The "Err flg" signal of the directly observed core does not reflect the comparison results and is masked in the process of test. The average number of experiments to determine pass/fail status of each core is same as the inter-core compare mode in [12], which is a function of the per core yield.…”

Section: Data-synchronous-comparator (Dsc) For Identical Coresmentioning

confidence: 99%

“…The responses of the cores are compared with the expect data which directly come from the external tester. For the quad-core AMD Opteron processor, an elaborate TAM with an on-chip comparison is presented [12] . It can enable comparing each core's responses to either the expected responses from the tester or to each other's responses.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Design for Testability Features of Godson-3 Multicore Microprocessor

Liu

et al. 2011

J. Comput. Sci. Technol.

View full text Add to dashboard Cite

This paper describes the design for testability (DFT) challenges and techniques of Godson-3 microprocessor, which is a scalable multicore processor based on the scalable mesh of crossbar (SMOC) on-chip network and targets high-end applications. Advanced techniques are adopted to make the DFT design scalable and achieve low-power and low-cost test with limited IO resources. To achieve a scalable and flexible test access, a highly elaborate test access mechanism (TAM) is implemented to support multiple test instructions and test modes. Taking advantage of multiple identical cores embedding in the processor, scan partition and on-chip comparisons are employed to reduce test power and test time. Test compression technique is also utilized to decrease test time. To further reduce test power, clock controlling logics are designed with ability to turn off clocks of non-testing partitions. In addition, scan collars of CACHEs are designed to perform functional test with low-speed ATE for speed-binning purposes, which poses low complexity and has good correlation results.

show abstract

Section: Data-synchronous-comparator (Dsc) For Identical Coresmentioning

confidence: 99%

Section: Data-synchronous-comparator (Dsc) For Identical Coresmentioning

confidence: 99%

Section: Data-synchronous-comparator (Dsc) For Identical Coresmentioning

confidence: 99%

Section: Data-synchronous-comparator (Dsc) For Identical Coresmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations