TeSR: A robust Temporal Self-Referencing approach for Hardware Trojan detection

Narasimhan, Seetharam; Wang, Xinmu; Du, Dongdong; Chakraborty, Rajat Subhra; Bhunia, Swarup

doi:10.1109/hst.2011.5954999

Cited by 107 publications

(43 citation statements)

References 6 publications

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“…Functional testing [4], [12], [13] verifies if the functionality of the IC under test is the same as specified. Side-channel fingerprinting [3], [7], [9] measures some side-channel signals (path delays, power, etc.) to distinguish Trojan-infected ICs from genuine ones.…”

Section: Backgroud a Trojans And Conutermeasuresmentioning

confidence: 99%

A security-aware design scheme for better hardware Trojan detection sensitivity

Bao

Xie

Srivastava

2015

2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)

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Due to the trend of outsourcing designs to foundries overseas, there has been an increasing threat of malicious modifications to the original integrated circuits (ICs), also known as hardware Trojans. Numerous countermeasures have been proposed. However, very little effort has been made to design-time strategies that help to make test-time or run-time detection of Trojans easier. In this paper, we characterize each cell's sensitivity to malicious modifications and develop an algorithm to select a subset of standard cells for a given circuit such that Trojans are easily detected using [1] when the circuit is synthesized on it. Experiments on 8 publicly available benchmarks show that using our method, we could detect on average 16.87% more Trojans with very small power/area overhead and no timing violations. I. INTRODUCTIONDue to the trend of outsourcing designs to foundries overseas, there has been an increasing concern in malicious inclusions in Integrated Circuit (IC) design also known as Hardware Trojans (HTs). HTs can change the IC's functionality, leak secret information, disable or destroy the entire chip and are thus very dangerous [6]. Numerous countermeasures have been proposed and most of them happen at test-time. These approaches compare the functionality or side-channel behavior (path delay, power, etc.) of the IC under test with that of a golden IC (Trojan-free IC). Some reverse-engineering (RE) based Trojan detection schemes also happen at test-time. They apply RE to the IC under test and recover the layout or gatelevel netlist, which is then compared with that of a golden IC. Run-time approaches have also been investigated. These approaches monitor the IC for unexpected changes in functionality or side-channel behavior at run-time. If such changes are detected, the run-time logic will bypass the malicious logic to prevent Trojans from doing any damage.Other than well-studied test-time and run-time approaches, very few design-time strategies that help in either preventing the insertion of Trojans or easier detection of Trojans are proposed [10]. We should notice that Trojan detection is not a easy job and a cooperation between design-time and testtime/run-time approaches is always preferred.In this paper, we propose an innovative design-time strategy that allows easier test-time detection of Trojans using RE based method such as [1]. Our technique relies on choosing a subset of standard cells that are more sensitive to Trojan insertion from a given technology library. By synthesizing the design using the subset, we can still utilize the existing library as well as the design tools. This enables early adoption of security techniques into the EDA tool flow. We choose [1] as our test-time approach because it can be used to verify that a chip is golden which is the underlying assumption of many other test-time approaches. Furthermore, since it uses RE, it is arguably among the strongest approaches to detect Trojans.We summarize the contributions of this paper as follows: 1) We characterize each standard ...

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Section: Backgroud a Trojans And Conutermeasuresmentioning

confidence: 99%

A security-aware design scheme for better hardware Trojan detection sensitivity

Bao

Xie

Srivastava

2015

2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)

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“…Functional testing [2]- [4] aims to detect HTs that change the functionality (primary outputs) of the IC from the intended one. Side-channel fingerprinting [11], [12] is an alternative approach that measures side channel signals (timing, power, etc.) and uses them to distinguish genuine ICs from Trojaninfested ones.…”

Section: Trojan Detection Techniquesmentioning

confidence: 99%

“…We used polynomial kernel function defined by (11) and chose degree d = 5. We used the default in LIBSVM γ = 0.2.…”

Section: A Experiments Setupmentioning

confidence: 99%

On application of one-class SVM to reverse engineering-based hardware Trojan detection

Bao

Forte

Srivastava

2014

Fifteenth International Symposium on Quality Electronic Design

113

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Due to design and fabrication outsourcing to foundries, the problem of malicious modifications to integrated circuits known as hardware Trojans has attracted attention in academia as well as industry. To reduce the risks associated with Trojans, researchers have proposed different approaches to detect them. Among these approaches, test-time detection approaches have drawn the greatest attention and most approaches assume the existence of a "golden model". Prior works suggest using reverse-engineering to identify such Trojan-free ICs for the golden model but they did not state how to do this efficiently. In this paper, we propose an innovative and robust reverseengineering approach to identify the Trojan-free ICs. We adapt a well-studied machine learning method, one-class support vector machine, to solve our problem. Simulation results using state-ofthe-art tools on several publicly available circuits show that our approach can detect hardware Trojans with high accuracy rate across different modeling and algorithm parameters.

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“…However, while the same symmetries can be exploited here, there are other symmetries that are not dependent on a signal bus, opening up for wider applicability. Continued work in [12] demonstrates that HTs can be detected as inconsistent power consumption when an IC repeatedly cycles along a closed loop in its finite state diagram but the HT, if using sequential logic, continues to change its state and expend different energies doing so. The authors contend, as we do, that the idea of a golden sample should be abandoned in favor of selfreferencing methods in order to greatly increase confidence in the presence of HTs despite growing inter-and intra-die variations throughout smaller technology nodes.…”

Section: Introductionmentioning

confidence: 98%

Hardware trojan detection by symmetry breaking in path delays

Yoshimizu¹

2014

2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)

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This paper discusses the detection of hardware Trojans (HTs) by their breaking of symmetries within integrated circuits (ICs), as measured by path delays. Typically, path delay or side channel methods rely on comparisons to a golden, or trusted, sample. However, golden standards are affected by interand intra-die variations which limit the confidence in such comparisons. Symmetry is a way to detect modifications to an IC with increased confidence by confirming subcircuit consistencies within as it was originally designed. The difference in delays from a given path to a set of symmetric paths will be the same unless an inserted HT breaks symmetry. Symmetry can naturally exist in ICs or be artificially added. We describe methods to find and measure path delays against symmetric paths, as well as the advantages and disadvantages of this method. We discuss results of examples from benchmark circuits demonstrating the detection of hardware Trojans.

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TeSR: A robust Temporal Self-Referencing approach for Hardware Trojan detection

Cited by 107 publications

References 6 publications

A security-aware design scheme for better hardware Trojan detection sensitivity

A security-aware design scheme for better hardware Trojan detection sensitivity

On application of one-class SVM to reverse engineering-based hardware Trojan detection

Hardware trojan detection by symmetry breaking in path delays

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