Ternary multiplication circuits using 4-input adder cells and carry look-ahead

Abstract

We introduce a new implementation of a ternary adder with four inputs and two outputs. This ternary adder reduces the number of digits in a multiplication compared with a binary multiplication. One advantage of the ternary adder is that four instead of three inputs within a binary representation will be summed up. In this paper we will compare the complexity of binary against ternary multipliers. Timing diagrams will be given for the binary and the ternary case with an optimal order of the adder inputs. Finally, we present a ternary carry look-ahead circuit for a further reduction of total time delay.

Fast Addition Using Balanced Ternary Counters Designed with CMOS Semi-Floating Gate Devices

“…There has been several attempts to implement arithmetic applications by using the ternary numbering system, but they lack commercial success [8] [3].…”

A Balanced Ternary Multiplication Circuit Using Recharged Semi-Floating Gate Devices

“…The so-called 'Brousentsov's Ternary Principle' of computer design was first realized in the Setun computer [1] and this computer used a 'ternary-symmetrical number system', which is another name for the balanced ternary notation. There has also been some other attempts to implement arithmetic applications which use the ternary numbering system, but they lack commercial success [2] [3].…”