Terabus: Terabit/Second-Class Card-Level Optical Interconnect Technologies

Schares, Laurent; Kash, J. A.; Doany, F. E.; Schow, Clint L.; Schuster, Christian; Kuchta, Daniel M.; Pepeljugoski, P.; Trewhella, J.M.; Baks, Christian; John, R.; Shan, Lei; Kwark, Young; Budd, R.; Chiniwalla, P.; Libsch, F.; Rosner, J.; Tsang, C. K.; Patel, C.S.; Schaub, J.D.; Dangel, R.; Horst, Folkert; Offrein, Bert Jan; Kucharski, D.; Guckenberger, D.; Hegde, S.; Nyikal, H.; Lin, Chia Wei; Tandon, Ashish; Trott, G.R.; Nystrom, M.; Bour, D. P.; Tan, Michael; Dolfi, David W.

doi:10.1109/jstqe.2006.881906

Cited by 213 publications

(81 citation statements)

References 41 publications

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“…Furthermore, the pitch of the waveguides on the board is typically fabrication limited and hence cannot be scaled to very fine Fig. 1(c) shows the schematic of terabus architecture with polymer waveguides at the board level fabricated at a 62.5 µm pitch [9,10]. A silicon based 'optical chip' converts the electrical signals to optical signal which is then relayed to the motherboard via a lens array and optical couplers.…”

Section: Current Methodologiesmentioning

confidence: 99%

Chip-to-chip interconnect integration technologies

Zia

Zhang

Yang

et al. 2016

IEICE Electron. Express

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With continuous increase in the off-chip bandwidth requirements, conventional interconnection methodologies are quickly becoming incapable of meeting the demand. Recent progress in silicon interposer and 3D integration technologies seek to alleviate some of these bottlenecks. This paper reviews the evolution of conventional interconnect methodologies and recent progress in platforms allowing high-bandwidth low-energy chip-tochip communication.

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Section: Current Methodologiesmentioning

confidence: 99%

Chip-to-chip interconnect integration technologies

Zia

Zhang

Yang

et al. 2016

IEICE Electron. Express

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“…Photonics dominates long-haul interconnects and is increasingly ubiquitous in metropolitan, storage, and local area networks. Photonic interconnects are becoming standard in data centers, and chip-to-chip optical links have been demonstrated [26]. This trend will naturally bring photonic interconnects into the chip stack, particularly since limited pin density and the power dissipation of global wires places significant constraints on performance and power.…”

Section: Photonic Technologymentioning

confidence: 99%

Corona: System Implications of Emerging Nanophotonic Technology

Vantrease

Schreiber

Monchiero

et al. 2008

2008 International Symposium on Computer Architecture

428

479

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We expect that many-core microprocessors will push performance per chip from the 10 gigaflop to the 10 teraflop range in the coming decade. To support this increased performance, memory and inter-core bandwidths will also have to scale by orders of magnitude. Pin limitations, the energy cost of electrical signaling, and the non-scalability of chip-length global wires are significant bandwidth impediments. Recent developments in silicon nanophotonic technology have the potential to meet these off-and on-stack bandwidth requirements at acceptable power levels.Corona is a 3D many-core architecture that uses nanophotonic communication for both inter-core communication and off-stack communication to memory or I/O devices. Its peak floating-point performance is 10 teraflops. Dense wavelength division multiplexed optically connected memory modules provide 10 terabyte per second memory bandwidth. A photonic crossbar fully interconnects its 256 low-power multithreaded cores at 20 terabyte per second bandwidth. We have simulated a 1024 thread Corona system running synthetic benchmarks and scaled versions of the SPLASH-2 benchmark suite. We believe that in comparison with an electrically-connected many-core alternative that uses the same on-stack interconnect power, Corona can provide 2 to 6 times more performance on many memoryintensive workloads, while simultaneously reducing power.

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“…While there is still considerable debate with regard to the precise role for photonics (Huang et al, 2003;Grubb et al, 2006;Tucker, 2008;Miller 2010), new power-efficient, cost-effective and broadband approaches are actively pursued. Supercomputers and data centers already deploy photonics to simplify and manage interconnection and are set to benefit from progress in parallel optical interconnects (Adamiecki et al, 2005;Buckman et al, 2004;Lemoff et al, 2004;Patel et al, 2003;Lemoff et al, 2005;Shares et al, 2006;Dangel et al, 2008). However, it is much more efficient to route the data over reconfigurable wiring, than to overprovision the optical wiring.…”

Section: Introductionmentioning

confidence: 99%

Photonic Integrated Semiconductor Optical Amplifier Switch Circuits

Williams

2011

Advances in Optical Amplifiers

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Terabus: Terabit/Second-Class Card-Level Optical Interconnect Technologies

Cited by 213 publications

References 41 publications

Chip-to-chip interconnect integration technologies

Chip-to-chip interconnect integration technologies

Corona: System Implications of Emerging Nanophotonic Technology

Photonic Integrated Semiconductor Optical Amplifier Switch Circuits

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