Terabit optical local area networks for multiprocessing systems

Szymański, Tomasz; Au, Albert; Lafrenière-Roula, Myriam; Tyan, Victor; Supmonchai, Boonchuay; Wong, James; Zerrouk, Belkacem; Obenaus, Stefan Thomas

doi:10.1364/ao.37.000264

Cited by 15 publications

(10 citation statements)

References 21 publications

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“…References [6] and [17] describe a network architecture demonstration that used an ONIC design similar to the one being proposed in this section. That ONIC design also used FPGAs and SERDES (SERializer/DESerializer) that can be reconfigured to support various network protocols.…”

Section: A Network Interface Card Overviewmentioning

confidence: 99%

RATS: Reactive Architectures

Christensen¹,

Kiamelev²,

Haney³

et al. 2004

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Public reporting burden for this collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing this collection of information. 12b. DISTRIBUTION CODE ABSTRACT (Maximum 200 Words)This project had two goals: To build an emulation prototype board for a tiled architecture and to demonstrate the utility of a global inter-chip free-space photonic interconnection fabric for polymorphous computer architectures (PCA). The free-space optics part of the project focused on two critical issues to validate the use of ultra-high-capacity global freespace interconnection fabrics for polymorphous computing architectures. These issues fell into the categories of interface issues and internal switch issues. The VCSEL-based free-space optical system was shown to be tolerant of misalignments, although electrical packaging problems prevented a full-performance demonstration. The optical links for the free-space system were demonstrated at 2.5 Gbps each with an inter-chip distance of about 10 cm. The project successfully demonstrated an optical inter-board fiber-based interconnect and intra-board free-space interconnect. The project also developed a prototype board that was demonstrated with an emulator of a tiled architecture.

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Section: A Network Interface Card Overviewmentioning

confidence: 99%

RATS: Reactive Architectures

Christensen¹,

Kiamelev²,

Haney³

et al. 2004

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“…A single-chip switch core where fiber-ribbons are coupled directly to optoelectronic devices on the chip is possible [29]. Attaching 32 incoming and 32 outgoing fiberribbons with 800 Mb/s per fiber translates to an aggregated bandwidth of 204 Gbit/s through the switch when eight fibers on each link are used for data.…”

Section: Optical Fibers and Electronic Crossbarsmentioning

confidence: 99%

Fiber-optic interconnection networks for signal processing applications

Jönsson

1999

Lecture Notes in Computer Science

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Abstract. In future parallel radar signal processing systems, with high bandwidth demands, new interconnection technologies are needed. The same reasoning can be made for other signal processing applications, e.g., those involving multimedia. Fiber-optic networks are a promising alternative and a lot of work have been done. In this paper, a number of fiber-optic interconnection architectures are reviewed, especially from a radar signal processing point-of-view. Two kinds of parallel algorithm mapping are discussed: (i) a chain of pipeline-stages mapped, more or less directly, one stage per computation node and (ii) SPMD (Same Program Multiple Data). Several network configurations, which are simplified due to the nature of the applications, are also proposed.

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“…These properties make possible new components such as the single-chip optoelectronic switch core reported in Ref. 13. In addition to the switch function the chip eliminates 32 OPTOBUS 800 Mbits/s per fiber transceivers.…”

Section: Implementation Aspectsmentioning

confidence: 99%

Two fiber-ribbon ring networks for parallel and distributed computing systems

Jönsson

1998

Opt. Eng

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Abstract. Ring networks made of fiber-ribbon point-to-point links are proposed. The first network is a control-channel based network in which one fiber in each link joins with others to form a control-channel ring. This ring improves performance of the network by sending medium access control information immediately before the data transmissions. High throughputs can be achieved in the network due to pipelining, i.e., several packets can travel through the network simultaneously but in different segments of the ring. The network can meet tough performance demands in, e.g., massively parallel signal processing systems, which is shown by example. Also, real-time demands can be met using slot reserving. The network, called CC-FPR (control-channel based fiberribbon pipeline ring), can be built today using off-the-shelf fiber optic components. The increasingly good price/performance ratio for fiberribbon links indicates a high potential for the success of the proposed kind of networks; a prototype is currently under development. The second network is similar to first except that it divides the network into two subnetworks, one for packet-switched traffic and one for circuit-switched traffic. When the main data flow in the network does not change rapidly, this is a good choice for a simple but powerful network.

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Terabit optical local area networks for multiprocessing systems

Cited by 15 publications

References 21 publications

RATS: Reactive Architectures

RATS: Reactive Architectures

Fiber-optic interconnection networks for signal processing applications

Two fiber-ribbon ring networks for parallel and distributed computing systems

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