Tensile Strained Selective Silicon Carbon Alloys for Recessed Source Drain Areas of Devices

Abstract

Si1-yCy films grown lattice matched into recessed source drain areas can produce a tensile strained Silicon channel, which in turn will enhance electron mobility. We demonstrate a Cyclical Deposition Etch (CDE) process that consists of a nonselective deposition, (epitaxial growth over the exposed crystalline Silicon areas of the source and drain and amorphous (a) or polycrystalline deposition over the dielectric areas) together with a subsequent selective removal of a-material from the insulator, with negligible removal of epitaxial material from source and drain areas. To make such an approach production worthy, two requirements are essential: 1) a high growth rate (GR) with a low a/epi GR ratio, and 2) a high etch rate (ER) with a high a/epi ER ratio. We focus on the integration and defect formation aspect of our CDE process on patterned substrates.

Throughput Considerations for In-Situ Doped Embedded Silicon Carbon Stressor Selectively Grown into Recessed Source Drain Areas of NMOS Devices

“…Process gas consumption and process gas utilization depend partially on (1) the dangling bond density on the Si surface and on (2) the precursor decomposition efficiency. The dangling bond density can be increased be decreasing the H/Cl surface coverage, which can be facilitated by eliminating/replacing the H 2 carrier gas with inert carrier gases such as N 2 , Ar or He or by increasing the H/Cl desorption from the surface in the form of molecular H 2 or HCl by increasing the surface temperature or through the use of a surface catalyst that enhances recombinative desorption from the surface.…”

“…In order to achieve a complementary effect in the nMOS device, there have been initial demonstrations of epitaxially grown SiC in the S/D regions to induce a uniaxial tensile strain in the channel (1). We have previously demonstrated the growth of high quality Si 1-y-z C y P z using a Cyclic Depoition and Etch (CDE) process that results in a net selective epitaxial growth (SEG) process having high substitutional C concentrations [C] sub up to 2.6% and high in-situ P doping concentrations up to 6 x 10 20 cm -3 (2,3). A combination of in-situ doped Si:C with high [C] sub in conjunction with a sub melt laser anneal (LSA) is promising (3).…”

Carbon- and Tin- Incorporated Source/Drain Stressors for CMOS Transistors

“…Our recent research focus has been on realizing strained n-FETs with enhanced levels of substitutional carbon concentration C sub , e.g. using selective epitaxy (13)- (14) or with advanced laser annealing technique (15). For ultra-thin body (UTB) and FinFET device architectures, the S/D recess etch is usually skipped due to lack of process margin for recess etch.…”

Very Low Temperature Tensile and Selective Si:P Epitaxy for Advanced CMOS Devices

“…Such a co-flow approach is not usable at temperatures lower than 600°C, as growth rates would be nil, then. A so-called Cyclic Deposition / Etch (CDE) strategy, with an alternating between non selective deposition steps with hydrogenated precursors and selective etch steps (of amorphous materials on dielectrics versus monocrystalline layers in active areas) with chlorinated precursors such as HCl or Cl2, is mandatory, then [5][6] [7]. NMOS device performances can also be improved through an increase of electron mobility in Si channels thanks to tensile strain [2] [8].…”