Temporal streams in commercial server applications

Wenisch, Thomas F.; Ferdman, Michael; Ailamaki, Anastasia; Falsafi, Babak; Moshovos, Andreas

doi:10.1109/iiswc.2008.4636095

Cited by 35 publications

(30 citation statements)

References 26 publications

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“…In practice, we find that this rarely happens as accesses to any given page are interleaved with a stream of accesses to other pages, hence destroying DRAM row buffer locality [1,46,47,57]. Keeping pages open and prioritizing accesses to an open page helps only to some extent, as accesses to different blocks within a page are often separated by a distance that is beyond the reach of the memory controller's scheduling window or occur in a datadependent fashion [51]. As row buffer locality is poorly exploited in existing designs, we find activations to be a major contributor to memory energy consumption.…”

Section: Introductionmentioning

confidence: 99%

BuMP: Bulk Memory Access Prediction and Streaming

Volos¹,

Picorel²,

Falsafi³

et al. 2014

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture

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Abstract-With the end of Dennard scaling, server power has emerged as the limiting factor in the quest for more capable datacenters. Without the benefit of supply voltage scaling, it is essential to lower the energy per operation to improve server efficiency. As the industry moves to lean-core server processors, the energy bottleneck is shifting toward main memory as a chief source of server energy consumption in modern datacenters. Maximizing the energy efficiency of today's DRAM chips and interfaces requires amortizing the costly DRAM page activations over multiple row buffer accesses.This work introduces Bulk Memory Access Prediction and Streaming, or BuMP. We make the observation that a significant fraction (59-79%) of all memory accesses fall into DRAM pages with high access density, meaning that the majority of their cache blocks will be accessed within a modest time frame of the first access. Accesses to high-density DRAM pages include not only memory reads in response to load instructions, but also reads stemming from store instructions as well as memory writes upon a dirty LLC eviction. The remaining accesses go to low-density pages and virtually unpredictable reference patterns (e.g., hashed key lookups). BuMP employs a low-cost predictor to identify high-density pages and triggers bulk transfer operations upon the first read or write to the page. In doing so, BuMP enforces high row buffer locality where it is profitable, thereby reducing DRAM energy per access by 23%, and improves server throughput by 11% across a wide range of server applications.

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Section: Introductionmentioning

confidence: 99%

BuMP: Bulk Memory Access Prediction and Streaming

Volos¹,

Picorel²,

Falsafi³

et al. 2014

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture

Self Cite

View full text Add to dashboard Cite

show abstract

“…On the other hand, Wenisch et al [32] and Tozun et. al [28] tie the micro-architectural behavior of the disk-based OLTP into specific code modules by presenting the breakdown of the cache misses into specific code parts of the traditional OLTP software stack at different code granularities.…”

Section: Oltp At the Micro-architectural Levelmentioning

confidence: 99%

Micro-architectural Analysis of In-memory OLTP

Sirin

Tözün

Porobic

et al. 2016

Proceedings of the 2016 International Conference on Management of Data

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Micro-architectural behavior of traditional disk-based online transaction processing (OLTP) systems has been investigated extensively over the past couple of decades. Results show that traditional OLTP mostly under-utilize the available micro-architectural resources. In-memory OLTP systems, on the other hand, process all the data in mainmemory, and therefore, can omit the buffer pool. In addition, they usually adopt more lightweight concurrency control mechanisms, cache-conscious data structures, and cleaner codebases since they are usually designed from scratch. Hence, we expect significant differences in micro-architectural behavior when running OLTP on platforms optimized for inmemory processing as opposed to disk-based database systems. In particular, we expect that in-memory systems exploit micro architectural features such as instruction and data caches significantly better than disk-based systems.This paper sheds light on the micro-architectural behavior of in-memory database systems by analyzing and contrasting it to the behavior of disk-based systems when running OLTP workloads. The results show that despite all the design changes, in-memory OLTP exhibits very similar microarchitectural behavior to disk-based OLTP systems: more than half of the execution time goes to memory stalls where L1 instruction misses and the long-latency data misses from the last-level cache are the dominant factors in the overall stall time. Even though aggressive compilation optimizations can almost eliminate instruction misses, the reduction in instruction stalls amplifies the impact of last-level cache data misses. As a result, the number of instructions retired per cycle barely reaches one on machines that are able to retire up to four for both traditional disk-based and new generation in-memory OLTP.

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“…The presence of address correlation in applications has been studied both quantitatively [6] and qualitatively [41] for scientific and commercial workloads. Studies find that the length of correlated streams can vary from two to several hundred [6,44], which implies that large amounts of storage are needed to prefetch these workloads effectively.…”

Section: Pointer-based Prefetchingmentioning

confidence: 99%

“…Because this correlation information grows in proportion to the application's memory footprint, the fundamental challenge for these prefetchers is the management of megabytes of off-chip correlation information [8,41,43]. Access to this off-chip meta-data increases prediction latency and memory traffic, which reduces the effectiveness of prefetching.…”

Section: Introductionmentioning

confidence: 99%

Linearizing irregular memory accesses for improved correlated prefetching

Jain

Lin

2013

Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture

111

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This paper introduces the Irregular Stream Buffer (ISB), a prefetcher that targets irregular sequences of temporally correlated memory references. The key idea is to use an extra level of indirection to translate arbitrary pairs of correlated physical addresses into consecutive addresses in a new structural address space, which is visible only to the ISB. This structural address space allows the ISB to organize prefetching meta-data so that it is simultaneously temporally and spatially ordered, which produces technical benefits in terms of coverage, accuracy, and memory traffic overhead.We evaluate the ISB using the Marss full system simulator and the irregular memory-intensive programs of SPEC CPU 2006 for both single-core and multi-core systems. For example, on a single core, the ISB exhibits an average speedup of 23.1% with 93.7% accuracy, compared to 9.9% speedup and 64.2% accuracy for an idealized prefetcher that overapproximates the STMS prefetcher, the previous best temporal stream prefetcher; this ISB prefetcher uses 32 KB of on-chip storage and sees 8.4% memory traffic overhead due to meta-data accesses. We also show that a hybrid prefetcher that combines a stride-prefetcher and an ISB with just 8 KB of on-chip storage exhibits 40.8% speedup and 66.2% accuracy.

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Temporal streams in commercial server applications

Abstract: Abstract

Cited by 35 publications

References 26 publications

BuMP: Bulk Memory Access Prediction and Streaming

BuMP: Bulk Memory Access Prediction and Streaming

Micro-architectural Analysis of In-memory OLTP

Linearizing irregular memory accesses for improved correlated prefetching

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