Temporal Readout Noise Analysis and Reduction Techniques for Low-Light CMOS Image Sensors

Abstract

Abstract-In this paper, an analytical noise calculation is presented to derive the impact of process and design parameters on 1/f and thermal noise for a low noise CIS readout chain. It is shown that dramatic noise reduction is obtained by using a thin oxide transistor as the source follower of a typical 4T pixel. This approach is confirmed by a test chip designed in a 180nm CIS CMOS process, and embedding small arrays of the proposed new pixels together with state-of-the-art 4T pixels for comparison. The new pixels feature a pitch of 7.5µm and a fill factor of 66%. A 0.4e-RMS input-referred noise and a 185µV/econversion gain are obtained. Compared to state-of-the-art pixels, also present onto the test chip, the RMS noise is divided by more than 2 and the conversion gain is multiplied by 2.2.

Ultra Low Noise CMOS Image Sensors

“…Fig. 5.10 shows that the 0.3 e − rms limit can be crossed if the thin oxide PMOS SF is combined with process optimizations reducing C P in the 180 nm process used in [9].…”

“…The continuous improvements of CIS, during the first decade of this century, led to the introduction and maturation of pinned photodiodes (PPDs) in CIS. The barrier of one photoelectron noise performance have been crossed using process modification [7] and even in standard CIS technology [8,9]. Process level optimization of CIS can today lead to a dynamic range over a hundred dB [10].…”

“…The charge transfer noise has been extensively studied for CCDs [63,64] because an efficient charge transfer is crucial in such devices. For 4T pixels based on PPDs, this issue is becoming an active point of research [62,65,59] with the read noise reaching deep subelectron levels in standard CIS process [66,9]. The main imperfections affecting the signal during the charge transfer from the PPD potential well to the sense node are shown in Fig.…”

“…buffers, sample-and-holds, and ADC. The column level amplifier also limits the bandwidth in order to minimize the thermal noise [9]. A switched capacitor amplifier is usually used.…”

“…A thinner oxide is expected to feature a better control of the gate over the channel and therefor a lower K F . The oxide trap density of thin oxide PMOS transistors and thick oxide NMOS transistors of different foundries and technology nodes have been compared in [9] based on data reported in design kits. This comparison showed that the thin oxide PMOS transistors generally feature a lower oxide trap density.…”