Temporal-Aware Mechanism to Detect Private Data in Chip Multiprocessors

Ros, Alberto; Cuesta, B.; Gomez, Maria E.; Robles, Antonio; Duato, J.

doi:10.1109/icpp.2013.70

Cited by 20 publications

(26 citation statements)

References 42 publications

(52 reference statements)

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“…Examples of run-time classifications are OS-based [7], [10], [11] (Section II-B1), TLB-based [32], or hardware-based [9], [12], [15], [33] methods. TLB-based methods are able to capture more private pages, but at the cost of extra traffic and complexity.…”

Section: Related Workmentioning

confidence: 99%

A Dual-Consistency Cache Coherence Protocol

Ros

Jimborean

2015

2015 IEEE International Parallel and Distributed Processing Symposium

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Abstract-Weak memory consistency models can maximize system performance by enabling hardware and compiler optimizations, but increase programming complexity since they do not match programmers' intuition. The design of an efficient system with an intuitive memory model is an open challenge. This paper proposes SPEL, a dual-consistency cache coherence protocol which simultaneously guarantees the strongest memory consistency model provided by the hardware and yields improvements in both performance and energy consumption. The design of the protocol exploits a compile-time identification of code regions which can be executed under a less restrictive, thus optimized protocol, without harming correctness. Outside these regions, code is executed under a more restrictive protocol which enforces sequential consistency. Compared to a standard directory protocol, we show improvements in performance of 24% and reductions in energy consumption of 32%, on average, for a 64-core chip multiprocessor.

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Section: Related Workmentioning

confidence: 99%

A Dual-Consistency Cache Coherence Protocol

Ros

Jimborean

2015

2015 IEEE International Parallel and Distributed Processing Symposium

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“…Alternatively, Hardavellas et al [9] and Li et al [10], [11] keep private blocks in the NUCA bank of the requesting processor to reduce the access latency to NUCA caches. This paper, which is an extension of the approach provided by Ros et al [12], proposes a mechanism that is capable of classifying data into a private-shared scheme while avoiding some of the major problems encountered on previous outlined techniques. Firstly, our mechanism relies on the TLB to keep the sharing status information, thus reducing storage requirements as it does not demand extra information in a directory-like structure [13], [14], [15] or in the page table [6], [7], [9], [16], [17].…”

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confidence: 99%

“…Note that the more private data detected, the more benefits can be obtained when using a classification scheme. This paper extends [12] by proposing a novel access prediction mechanism to avoid premature page invalidations of TLB entries and cache blocks when applying decay techniques. In [12], low decay values cause so many invalidations that makes the high detection of private blocks unattractive.…”

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confidence: 99%

“…This paper extends [12] by proposing a novel access prediction mechanism to avoid premature page invalidations of TLB entries and cache blocks when applying decay techniques. In [12], low decay values cause so many invalidations that makes the high detection of private blocks unattractive. However, in this paper, we force pages migrating frequently from a core to another to become shared.…”

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Efficient TLB-Based Detection of Private Pages in Chip Multiprocessors

Esteve

Ros

Gomez

et al. 2016

IEEE Trans. Parallel Distrib. Syst.

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Abstract-Most of the data referenced by sequential and parallel applications running in current chip multiprocessors are referenced by a single thread, i.e., private. Recent proposals leverage this observation to improve many aspects of chip multiprocessors, such as reducing coherence overhead or the access latency to distributed caches. The effectiveness of those proposals depends to a large extent on the amount of detected private data. However, the mechanisms proposed so far do not consider neither thread migration nor the private use of data within different application phases. As a result, a considerable amount of private data is not detected. In order to increase the detection of private data, we propose a TLB-based mechanism that is able to account for both thread migration and application phases. Simulation results show that the average number of pages detected as private significantly increases from 43% in previous proposals up to 79% in ours while keeping a reasonable TLB miss rate. Furthermore, when our proposal is used to deactivate the coherence for private data in a directory protocol, it improves execution time by 13.5%, on average, with respect to previous techniques.

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“…Coverage misses [67] are those caused by invalidation on the directory cache due to the limited capacity, which cause an eviction of the block entry in the private caches. Moreover, we discern Flushing [68] misses, which are those caused by invalidated or evicted TLB entries, which in turn induces cache invalidations when employing a TLB-based classification approach.…”

Section: Metricsmentioning

confidence: 99%

Design of Efficient TLB-based Data Classification Mechanisms in Chip Multiprocessors

García¹

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AcknowledgmentCuatro años de esfuerzo dan para mucho. Echándo la vista atrás, muchas son las personas que me han apoyado, muchos los que me han escuchado. Gracias a todos.A Ramón y Lola. Sin ellos, sin su apoyo y su amor, no habría llegado hasta aquí. Sin su inspiración no habría siquiera empezado el camino. Ellos plantaron la semilla de la curiosidad, tan necesaria para superar la frustración y las dificultades a las que todo investigador tiene que enfrentar en su camino.A Víctor. Hermano y amigo. El espejo en el que me miro. Me has dado fuerza en cada etapa de mi vida. Gracias por todo. Habrá que pensar una buena ruta en bici para celebrarlo.A Carla. Por su paciencia, por su ayuda, por respaldarme cuando lo he necesitado. Siempre me has animado a seguir adelante y has permanecido a mi lado en cada etapa del doctorado. Más que eso, eres uno de los pilares principales de mi vida.A Salomé, Eloy y Sergio. Por quererme y aceptarme como uno más de la familia. Realmente yo lo siento del mismo modo. Gracias.A mis amigos. Samuel, Eduardo, Manolo. Ya sea jugando a algún juego, organizándo viajes juntos, o saliendo de fiesta o a tomar algo, siempre habéis estado ahí, siendo partícipes de mis logros y mis frustraciones. Tanto como yo de las vuestras. Y espero que siga siendo así por muchos, muchos años.Allá por 2007 empezaba mi andadura por la universidad, hace ya diez años.Ésta ha sido mi segunda casa, y le debo mucho. Y tengo muchos que agradecer también a toda la gente que he conocido en este etapa. Incluyendoéstaúltima fase en el Grupo de Arquitecturas Paralelas.Por supuesto y ante todo a mis directores, Alberto, Antonio y Maria Engracia. Me habéis guiado e inspirado, desafiado y ayudado en cada etapa de mi doctorado. Vuestra paciencia y esfuerzo han sido claves para la consecución de este trabajo. He aprendido mucho durante estos años. No sólo en materia de arquitectura de computadores, sino también en investigación científica; a amarla, a observar los pequeños detalles, a analizar los datos y entender qué esta ocurriendo para así poder seguir avanzando. Ellos han cambiado mi vida, profesional y personal, para siempre.A Núria, Salva y Eduardo. No nos vemos tanto como antes, nuestras vidas, sus obligaciones, nos alejan. Pero aún nos quedarán esas tardes de cervezas para ponernos al día. Siempre.A mis compañeros de laboratorio. José Vicente, José María, Migue, Vicent, Joan, Fran, Javi, Roberto, Carlos, Santi, y un largo etcétera. A los que se fueron, Knut, Mario, Crispín. Tantos y tantos. A todos os debo algo. Lo que ha unido el BoardGameArena que no lo separen nuestras exitosas carreras en el extranjero, como un tren de mercancías desbocado y sin frenos. Y por supuesto a Ricardo. El verdadero pilar del laboratorio, en lo técnico y en lo personal. Tu increible paciencia y dedicación te hacen pieza central del trabajo de todos nosotros en el grupo.

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Temporal-Aware Mechanism to Detect Private Data in Chip Multiprocessors

Cited by 20 publications

References 42 publications

A Dual-Consistency Cache Coherence Protocol

A Dual-Consistency Cache Coherence Protocol

Efficient TLB-Based Detection of Private Pages in Chip Multiprocessors

Design of Efficient TLB-based Data Classification Mechanisms in Chip Multiprocessors

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