Temperature-insensitive analog vector-by-matrix multiplier based on 55 nm NOR flash memory cells

Guo, Xin; Bayat, F. Merrikh; Prezioso, M.; Chen, Y.; Nguyen, Bao Quoc; Do, Nhan; Strukov, Dmitri B.

doi:10.1109/cicc.2017.7993628

Cited by 57 publications

(46 citation statements)

References 9 publications

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“…e details on the redesigned structure, static and dynamic I -V characteristics, analog retention, and noise of the oating gate transistors, as well as results of high precision tuning experiments can be found in Ref. [15]. e network, which features 10 inputs and 10 hidden-layer / output neurons, is implemented with two identical 10 × 20 arrays of supercells, CMOS circuits for the pipelined VMM operation and rectify-linear transfer function as described in previous subsection, as well as CMOS circuitry for programming and erasure of the FG cells ( Fig.…”

Section: Embedded Nor Flash Memory Implementationmentioning

confidence: 99%

“…e most promising implementations of low to medium precision VMMs are arguably based on analog and mixed-signal circuits [12]. In a current-mode implementation, the multi-bit inputs are encoded as analog voltages/currents, or digital voltage pulses [13], which are applied to one set of (e.g., row) electrodes of the array with adjustable conductance cross-point devices, such as memristors [7,13] or oating-gate memories [5,14,15], while VMM outputs are represented by the currents owing into the column electrodes. e main drawback of this approach is energy-hungry and area-demanding peripheral circuits, which, e.g.…”

Section: Introductionmentioning

confidence: 99%

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Energy-Efficient Time-Domain Vector-by-Matrix Multiplier for Neurocomputing and Beyond

Bavandpour

Mahmoodi

Strukov

2019

IEEE Trans. Circuits Syst. II

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We propose an extremely energy-e cient mixed-signal approach for performing vector-by-matrix multiplication in a time domain. In such implementation, multi-bit values of the input and output vector elements are represented with time-encoded digital signals, while multi-bit matrix weights are realized with current sources, e.g. transistors biased in subthreshold regime. With our approach, multipliers can be chained together to implement large-scale circuits completely in a time domain. Multiplier operation does not rely on energy-taxing static currents, which are typical for peripheral and input/output conversion circuits of the conventional mixed-signal implementations. As a case study, we have designed a multilayer perceptron, based on two layers of 10 × 10 four-quadrant vectorby-matrix multipliers, in 55-nm process with embedded NOR ash memory technology, which allows for compact implementation of adjustable current sources. Our analysis, based on memory cell measurements, shows that at high computing speed the drain-induced barrier lowering is a major factor limiting multiplier precision to ∼ 6 bit. Post-layout estimates for a conservative 6-bit digital input/output N × N multiplier designed in 55 nm process, including I/O circuitry for converting between digital and time domain representations, show ∼ 7 fJ/Op for N > 200, which can be further lowered well below 1 fJ/Op for more optimal and aggressive design.

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Section: Embedded Nor Flash Memory Implementationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Energy-Efficient Time-Domain Vector-by-Matrix Multiplier for Neurocomputing and Beyond

Bavandpour

Mahmoodi

Strukov

2019

IEEE Trans. Circuits Syst. II

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“…For this purpose, NOR memory arrays developed with a 180 nm technology by Silicon Storage Technology, Inc. (SST) [52] are chosen in refs. [53][54][55][56]. The basic memory cell, as depicted in Figure 7a, features a highly asymmetric structure presenting a floating gate only near the source side, with the gate stack at the drain side made only of the tunneling oxide.…”

Section: Memory Transistors As Synaptic Devices In Artificial Neural mentioning

confidence: 99%

“…In this regard, some preliminary results about MVM were already presented in ref. [56]. Although this solution based on re-routing commercially available NOR arrays appears promising, it comes together with its main drawback consisting in the increased area occupancy (the single-cell area in the modified array is 2.3 times larger than the original one).…”

Section: Memory Transistors As Synaptic Devices In Artificial Neural mentioning

confidence: 99%

Memristive and CMOS Devices for Neuromorphic Computing

et al. 2020

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Neuromorphic computing has emerged as one of the most promising paradigms to overcome the limitations of von Neumann architecture of conventional digital processors. The aim of neuromorphic computing is to faithfully reproduce the computing processes in the human brain, thus paralleling its outstanding energy efficiency and compactness. Toward this goal, however, some major challenges have to be faced. Since the brain processes information by high-density neural networks with ultra-low power consumption, novel device concepts combining high scalability, low-power operation, and advanced computing functionality must be developed. This work provides an overview of the most promising device concepts in neuromorphic computing including complementary metal-oxide semiconductor (CMOS) and memristive technologies. First, the physics and operation of CMOS-based floating-gate memory devices in artificial neural networks will be addressed. Then, several memristive concepts will be reviewed and discussed for applications in deep neural network and spiking neural network architectures. Finally, the main technology challenges and perspectives of neuromorphic computing will be discussed.

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“…As an implementation approach other than digital processors, use of analog operation in CMOS VLSI circuits is a promising method for achieving an extremely low power consumption operation of such a calculation task [5,16,22,21]. Although the calculation precision is limited due to the non-idealities of analog operation such as noise and device mismatches, the neural network models and circuits can be designed to be robust to such non-idealities [24,10,7]. On the other hand, in the research field of ANN models, low-precision neural networks have been proposed and their comparable performance has been demonstrated, mainly in applications of image recognition [3,9].…”

Section: Introductionmentioning

confidence: 99%

Time-Domain Weighted-Sum Calculation for Ultimately Low Power VLSI Neural Networks

Wang

Tamukoh

Matsukawa

2016

Neural Information Processing

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A time-domain analog weighted-sum calculation model is proposed based on an integrate-and-fire-type spiking neuron model. The proposed calculation model is applied to multi-layer feedforward networks, in which weighted summations with positive and negative weights are separately performed in each layer and summation results are then fed into the next layers without their subtraction operation. We also propose very large-scale integrated (VLSI) circuits to implement the proposed model. Unlike the conventional analog voltage or current mode circuits, the time-domain analog circuits use transient operation in charging/discharging processes to capacitors. Since the circuits can be designed without operational amplifiers, they can operate with extremely low power consumption. However, they have to use very high resistance devices on the order of GΩ. We designed a proof-of-concept (PoC) CMOS VLSI chip to verify weighted-sum operation with the same weights and evaluated it by post-layout circuit simulation using 250-nm fabrication technology. High resistance operation was realized by using the subthreshold operation region of MOS transistors. Simulation results showed that energy efficiency for the weighted-sum calculation was 290 TOPS/W, more than one order of magnitude higher than that in state-of-the-art digital AI processors, even though the minimum width of interconnection used in the PoC chip was several times larger than that in such digital processors. If state-of-the-art VLSI technology is used to implement the proposed model, an energy efficiency of more than 1,000 TOPS/W will be possible. For practical applications, development of emerging analog memory devices such as ferroelectric-gate FETs is necessary.

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Temperature-insensitive analog vector-by-matrix multiplier based on 55 nm NOR flash memory cells

Cited by 57 publications

References 9 publications

Energy-Efficient Time-Domain Vector-by-Matrix Multiplier for Neurocomputing and Beyond

Energy-Efficient Time-Domain Vector-by-Matrix Multiplier for Neurocomputing and Beyond

Memristive and CMOS Devices for Neuromorphic Computing

Time-Domain Weighted-Sum Calculation for Ultimately Low Power VLSI Neural Networks

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