Temperature Effect on Dielectric Breakdown and Charges Retention of Nanocrystalline Cadmium Selenide Embedded Zr-Doped HfO2 High- ${k}$ Dielectric Thin Film

Zhang, Shumao; Kuo, Yue

doi:10.1109/tdmr.2016.2617682

Cited by 7 publications

(15 citation statements)

References 40 publications

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“…32 The negative shift of the C-V curve is due to the generation of holetrapping defects in the breakdown process. 33 The original O 2 PDA capacitor has better electrical properties than those of the original N 2 PDA capacitor. For example, in addition to a larger V BD as shown in Fig.…”

Section: Resultsmentioning

confidence: 99%

Post Deposition Annealing Atmosphere Effect on Performance of Solid State Incandescent Light Emitting Device

Zhang

Kuo

2017

ECS J. Solid State Sci. Technol.

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Electrical and optical properties of solid state incandescent light emitting devices made from MOS capacitors of the same Zr-doped HfO 2 high-k film but two different post deposition annealing atmospheres have been investigated. Compared with the N 2 annealed sample, the O 2 annealed capacitor has a thicker and more SiO x -rich interface layer, lower defect densities, a larger dielectric breakdown strength, and a lower leakage current. Light emitted from the solid-state incandescent light emitting device made from the O 2 annealed capacitor has a high intensity and slightly more blue component than that made from the N 2 annealed capacitor due to the higher temperature of the conductive path. The former contains more Si and O elements in conductive paths than the latter does, which can be used to explain the difference in their electrical and optical characteristics. The post deposition atmosphere affected the original high-k stack's material and physical properties, which influences the formation and material composition of conductive paths and eventually the light emission characteristics. If incandescent and fluorescent light lamps are replaced with solidstate light emitting devices (LEDs), the energy consumption from lighting in the United States can be saved by about 38%.1 LEDs are usually made of direct-bandgap semiconductor materials prepared in the p-n junction or quantum well (QW) structure.2,3 They require the growth of high quality compound semiconductor epitaxy layers on single crystal substrates. The process is expensive and tedious. 1-3The light emission principle is the electron-hole or exciton-exciton recombination. The energy of the emitted light is equivalent to that of the bandgap energy of the semiconductor material.1-3 Therefore, the broad-band light cannot be emitted from a single LED. The white light can be generated using 3 different kinds of LEDs, i.e., red, green, and blue light emitting, or a blue LED in combination with a phosphor layer. 4,5 CdSe/ZnS core-shell nanocrystals have been used to convert the blue/UV light into the green/red light, which is also a method of generating the white light. 6,7 However, the size of the nanocrystal has to be tightly controlled to emit a specific color, which is difficult to achieve. 7 The semiconductor based LED is often subject to the "droop" failure mechanism that shortens the lifetime. 8 It is desirable to have a LED that emits the broad band white light from a single device and can be fabricated with the IC-compatible process with a long lifetime. Recently, Kuo's group reported a new type of solid-state incandescent LED (SSI-LED) that emitted the warm white light similar to that of the incandescent bulb.9-16 The light emitting principle of the SSI-LED is the thermal excitation of the nano-sized conductive path from the passage of a current. [9][10][11][12][13][14][15][16] It is made from a MOS capacitor composed of an amorphous high-k dielectric thin film, such as Zr-doped HfO 2 (ZrHfO), HfO x , or WO x , on a p-type Si wafer.9-16 These high-k...

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Section: Resultsmentioning

confidence: 99%

Post Deposition Annealing Atmosphere Effect on Performance of Solid State Incandescent Light Emitting Device

Zhang

Kuo

2017

ECS J. Solid State Sci. Technol.

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“…After the dielectric breakdown, conductive paths are formed in the high-k stack. 11 For the control sample, since monitored at V g = 0 V, there is a small negative J relax , which shows as the polarity change, due to the workfunction difference of the ITO gate and Si substrate or the instrument offset. 11,40 However, for the nc-CdS embedded sample, the polarity remains the same but the magnitude of the J relax decreases, which is due to the gradual release of the trapped holes from the nc-CdS sites.…”

Section: Resultsmentioning

confidence: 99%

“…have been embedded in the gate dielectric to achieve the large memory window and long charge retention time. [4][5][6][7][8][9][10][11][12] These devices often suffer from the frequency dispersion problem due to defects at the nanocrystal/dielectric interface. 7,8,10,12,13 CdS is an n-type semiconductor material with a large electron affinity of 4.3 eV, which makes it a potential useful charge trapping medium in the dielectric layer.…”

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confidence: 99%

Memory Functions of Cadmium Sulfide Embedded Zr-Doped HfO₂High-k Dielectrics

Zhang

Kuo

2018

ECS J. Solid State Sci. Technol.

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Nonvolatile memory characteristics of CdS embedded Zr-doped HfO 2 high-k MOS capacitors have been studied. The n-type nature of the CdS caused the preference of hole-trapping in the bulk high-k layer. The lack of frequency dispersion of the capacitance-voltage curve was due to the passivation of defects at the CdS/high-k interface. The hole trapping/detrapping mechanism was verified with the current-voltage measurement. The loosely trapped holes were quickly released upon the release of the stress voltage. The embedded CdS layer maintained the hole trapping capability after the dielectric breakdown. About half of the originally trapped charges were retained after releasing the stress voltage for 10 years. The CdS embedded samples showed good memory and charge retention characteristics. Therefore, the CdS embedded Zr-doped HfO 2 gate dielectric structure is suitable for low voltage nonvolatile memory applications.

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“… 4 For smaller channel widths and higher stacks, the thickness of the thin films should be decreased, 7 which makes the thin films more vulnerable to various thermomechanical failures, such as bending, cracking, and, particularly, interfacial delamination. 8 , 9 These factors eventually lead to the catastrophic failure of the devices. 4 …”

Section: Introductionmentioning

confidence: 99%

“…Among the various nanostructures, nanoplates with oxide or nitride/nitride/metal multilayers are one of the essential components in thin-film transistors since oxide, nitride, and metal layers are used as the gate dielectric, adhesion layer, and gate metal in metal/insulator/semiconductor (MIS) structures, respectively . For smaller channel widths and higher stacks, the thickness of the thin films should be decreased, which makes the thin films more vulnerable to various thermomechanical failures, such as bending, cracking, and, particularly, interfacial delamination. , These factors eventually lead to the catastrophic failure of the devices …”

Section: Introductionmentioning

confidence: 99%

Interfacial Delamination at Multilayer Thin Films in Semiconductor Devices

et al. 2022

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With the evolution of semiconducting industries, thermomechanical failure induced in a multilayered structure with a high aspect ratio during manufacturing and operation has become one of the critical reliability issues. In this work, the effect of thermomechanical stress on the failure of multilayered thin films on Si substrates was studied using analytical calculations and various thermomechanical tests. The residual stress induced during material processing was calculated based on plate bending theory. The calculations enabled the prediction of the weakest region of failure in the thin films. To verify our prediction, additional thermomechanical stress was applied to induce cracking and interfacial delamination by various tests. We assumed that, when accumulated thermomechanical-residual and externally applied mechanical stress becomes larger than a critical value the thin-film cracking or interfacial delamination will occur. The test results agreed well with the prediction based on the analytical calculation in that the film with maximum tensile residual stress is the most vulnerable to failure. These results will provide useful analytical and experimental prediction tools for the failure of multilayered thin films in the device design stage.

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Temperature Effect on Dielectric Breakdown and Charges Retention of Nanocrystalline Cadmium Selenide Embedded Zr-Doped HfO2 High- ${k}$ Dielectric Thin Film

Cited by 7 publications

References 40 publications

Post Deposition Annealing Atmosphere Effect on Performance of Solid State Incandescent Light Emitting Device

Post Deposition Annealing Atmosphere Effect on Performance of Solid State Incandescent Light Emitting Device

Memory Functions of Cadmium Sulfide Embedded Zr-Doped HfO₂High-k Dielectrics

Interfacial Delamination at Multilayer Thin Films in Semiconductor Devices

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Temperature Effect on Dielectric Breakdown and Charges Retention of Nanocrystalline Cadmium Selenide Embedded Zr-Doped HfO2 High- ${k}$ Dielectric Thin Film

Cited by 7 publications

References 40 publications

Post Deposition Annealing Atmosphere Effect on Performance of Solid State Incandescent Light Emitting Device

Post Deposition Annealing Atmosphere Effect on Performance of Solid State Incandescent Light Emitting Device

Memory Functions of Cadmium Sulfide Embedded Zr-Doped HfO2High-k Dielectrics

Interfacial Delamination at Multilayer Thin Films in Semiconductor Devices

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Memory Functions of Cadmium Sulfide Embedded Zr-Doped HfO₂High-k Dielectrics