2018
DOI: 10.1007/s10825-018-1212-y
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Temperature-dependent short-channel parameters of FinFETs

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Cited by 11 publications
(4 citation statements)
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“…On the other hand, intrinsic gain, denoted as A v and calculated as the ratio of transconductance to output conductance [2], is a critical parameter. Maximizing the intrinsic gain involves increasing G m while decreasing G d .…”
Section: Resultsmentioning
confidence: 99%
See 1 more Smart Citation
“…On the other hand, intrinsic gain, denoted as A v and calculated as the ratio of transconductance to output conductance [2], is a critical parameter. Maximizing the intrinsic gain involves increasing G m while decreasing G d .…”
Section: Resultsmentioning
confidence: 99%
“…Therefore, the semiconductor industry is searching for an alternative to the MOSFET, which overcomes the problems of MOSFET and withstands the negative impacts of downscaling [1]. With down-scaling of device attributes, various undesired side effects are experienced, called non-deal effects or short channel effects (SCEs) [2]. A few non-ideal effects in MOSFET are subthreshold swing (SS), draininduced barrier lowering (DIBL), variation of threshold voltage (V th ), leakage current, tunneling current, and channel length modulation, mobility variation, velocity saturation, etc.…”
Section: Introductionmentioning
confidence: 99%
“…However, MOSFET faces various unwanted problems owing to reducing the device dimensions. The overscaling of device dimensions in MOSFET introduces a non-ideal effect called short channel effects (SCEs) [39]. These SCEs affect the device's efficiency.…”
Section: Transistor Technology In Neuromorphic Devices a Evolution Of...mentioning
confidence: 99%

FETs for Analog Neural MACs

Das,
Rajalekshmi,
Pallathuvalappil
et al. 2024
IEEE Access
Self Cite
“…Reference [31] investigated the influence of temperature on the linearity and harmonic distortion performance of asymmetric under‐lapped FinFET (U‐FinFET) and shows that distortion is optimized in the sub‐threshold region at high temperature. Das et al reported 32 the gate overlap to drain and source of FinFET reduce the leakage current and improve drain characteristics with a minimized value of SCEs. Reference [33] studied and explored the impact of the temperature variation of FinFET to analyze the short channel effect and observed that the device is more immune at low temperature.…”
Section: Introductionmentioning
confidence: 99%