Temperature-dependent Fowler-Nordheim electron barrier height in SiO2/4H-SiC MOS capacitors

Fiorenza, Patrick; Vivona, Marilena; Iucolano, Ferdinando; Severino, Andrea; Lorenti, Simona; Nicotra, Giuseppe; Bongiorno, Corrado; Giannazzo, Filippo; Roccaforte, Fabrizio

doi:10.1016/j.mssp.2017.11.024

Cited by 29 publications

(13 citation statements)

References 25 publications

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“…The higher valence band offset and the lateral confinement of the TD produces the creation of a quantum well. Considering the ideal conduction contribution -i.e., the ideal Fowler-Nordheim (FN) tunnelling [24] and the quantum confinement that inhibits the FN tunnelling from the bottom of the quantum well [25] -the oxide electric field produces a minor increase of the hole current through the insulator layer. Besides the calculated increase of the electric field due to the TD band gap narrowing, also the surface morphology plays a role [26].…”

Section: Resultsmentioning

confidence: 99%

Understanding the role of threading dislocations on 4H-SiC MOSFET breakdown under high temperature reverse bias stress

et al. 2020

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The origin of dielectric breakdown was studied on 4H-SiC MOSFETs that failed after three months of high temperature reverse bias (HTRB) stress. A local inspection of the failed devices demonstrated the presence of a threading dislocation (TD) at the breakdown location. The nanoscale origin of the dielectric breakdown was highlighted with advanced high-spatial-resolution scanning probe microscopy (SPM) techniques. In particular, SPM revealed the conductive nature of the TD and a local increase of the minority carrier concentration close to the defect. Numerical simulations estimated a hole concentration 13 orders of magnitude larger than in the ideal 4H-SiC crystal. The hole injection in specific regions of the device explained the failure of the gate oxide under stress. In this way, the key role of the TD in the dielectric breakdown of 4H-SiC MOSFET was unambiguously demonstrated.

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Section: Resultsmentioning

confidence: 99%

Understanding the role of threading dislocations on 4H-SiC MOSFET breakdown under high temperature reverse bias stress

et al. 2020

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“…with where ϕ t is the electron emission barrier height from the trap states, ε AlN is the relative dielectric permittivity of the gate insulator at high frequency ( ε AlN 4.77 [ 49 ]), ε 0 is the permittivity of free space, and C is a constant. The validity of the PF emission fitting was verified by checking the temperature dependence of the linear coefficient m ( T ) obtained from the lineal fit of the PF plots ln( J / E ) as a function of E 1/2 [ 50 ], which is shown in Fig. 10 .…”

Section: Resultsmentioning

confidence: 99%

Thickness Dependence on Interfacial and Electrical Properties in Atomic Layer Deposited AlN on c-plane GaN

2018

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The interfacial and electrical properties of atomic layer deposited AlN on n-GaN with different AlN thicknesses were investigated. According to capacitance–voltage (C–V) characteristics, the sample with a 7.4-nm-thick AlN showed the highest interface and oxide trap densities. When the AlN thickness was 0.7 nm, X-ray photoelectron spectroscopy (XPS) spectra showed the dominant peak associated with Al–O bonds, along with no clear AlN peak. The amount of remained oxygen atoms near the GaN surface was found to decrease for the thicker AlN. However, many oxygen atoms were present across the AlN layer, provided the oxygen-related defects, which eventually increased the interface state density. The barrier inhomogeneity with thermionic emission (TE) model was appropriate to explain the forward bias current for the sample with a 7.4-nm-thick AlN, which was not proper for the sample with a 0.7-nm-thick AlN. The reverse leakage currents for both the samples with 0.7- and 7.4-nm-thick AlN were explained better using Fowler–Nordheim (FN) rather than Poole–Frenkel emissions.

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“…Figure 7 shows the comparison between the conductivity profile on the as deposited (black line) and N2O annealed (blue line) samples, determined using the SSRM. Fabrication details can be found in Reference [55]. As can be seen, the number of free carriers in the nitridated sample is increased by more than one order of magnitude in a region about 10 nm wide from the SiO2/4H-SiC interface [47,51].…”

Section: Effects Of Counter Doping and Interface Stressmentioning

confidence: 98%

Characterization of SiO2/4H-SiC Interfaces in 4H-SiC MOSFETs: A Review

2019

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This paper gives an overview on some state-of-the-art characterization methods of SiO2/4H-SiC interfaces in metal oxide semiconductor field effect transistors (MOSFETs). In particular, the work compares the benefits and drawbacks of different techniques to assess the physical parameters describing the electronic properties and the current transport at the SiO2/SiC interfaces (interface states, channel mobility, trapping phenomena, etc.). First, the most common electrical characterization techniques of SiO2/SiC interfaces are presented (e.g., capacitance- and current-voltage techniques, transient capacitance, and current measurements). Then, examples of electrical characterizations at the nanoscale (by scanning probe microscopy techniques) are given, to get insights on the homogeneity of the SiO2/SiC interface and the local interfacial doping effects occurring upon annealing. The trapping effects occurring in SiO2/4H-SiC MOS systems are elucidated using advanced capacitance and current measurements as a function of time. In particular, these measurements give information on the density (~1011 cm−2) of near interface oxide traps (NIOTs) present inside the SiO2 layer and their position with respect to the interface with SiC (at about 1–2 nm). Finally, it will be shown that a comparison of the electrical data with advanced structural and chemical characterization methods makes it possible to ascribe the NIOTs to the presence of a sub-stoichiometric SiOx layer at the interface.

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Temperature-dependent Fowler-Nordheim electron barrier height in SiO2/4H-SiC MOS capacitors

Cited by 29 publications

References 25 publications

Understanding the role of threading dislocations on 4H-SiC MOSFET breakdown under high temperature reverse bias stress

Understanding the role of threading dislocations on 4H-SiC MOSFET breakdown under high temperature reverse bias stress

Thickness Dependence on Interfacial and Electrical Properties in Atomic Layer Deposited AlN on c-plane GaN

Characterization of SiO2/4H-SiC Interfaces in 4H-SiC MOSFETs: A Review

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