Temperature dependence on the contact size of GeSbTe films for phase change memories

Abstract

In this study, a three-dimensional electro-thermal time-domain simulation is developed for dynamic thermal analysis of Phase change memories (PCMs). The geometry effects of the GeSbTe (GST) materials and the TiN heater are explored through a series of numerical examinations. It is found that the contact size of the GST significantly alters the maximum temperature of the PCMs, compared with the height of the GST films. The heater's aspect ratio also dominates the maximum temperature of the GST material, and the effect of the heater's thickness on the temperature is more evident than its height. One conformal bi-layer GST structure with different electric and thermal conductivities on the GST layers is examined for different applied currents to extract the curve of resistances versus applied currents.

The Design of Rewritable Ultrahigh Density Scanning-Probe Phase-Change Memories

“…For the underlayer, which acts as the return electrode for the potential applied to the tip, we require a good electrical conductivity coupled with a relatively modest thermal conductivity (the latter requirement to retain enough heat in the stack to meet the minimum temperature requirements). A good choice is likely to be TiN, which is already used as electrode material in PCRAM devices and can be prepared with a range of suitable thermal and electrical conductivities [15,[34][35][36]. Thus we restrict the parameter search for underlayer properties to those corresponding to typical TiN thin films.…”

“…In Fig. 2 [34][35][36]. The values used for other relevant material parameters are given in Table I.…”

“…For the TiN thermal conductivity of 12 Wm -1 K -1 the contours for melting at point D A and exceeding a maximum temperature of 1000 0 C do not overlap, which would imply that in this case, whatever the thermal conductivity of the DLC capping layer (within the range studied) or the applied voltage, we could not write an amorphous bit that extends a significant depth into the GST layer without exceeding 1000 0 C in the capping layer. However, reducing the thermal conductivity of the underlayer to 3 Wm -1 K -1 , still a reasonable value for actual TiN thin films (see [35] for example), moves the melting contour at D A to lower voltages, such that all the maximum/minimum temperature requirements set previously for the writing of amorphous marks can now be met for moderate voltages and realistic values for the thermal and electrical conductivity of the DLC capping layer. Since thermal and electrical conductivity are usually linked (e.g.…”

“…7(a) where, for the first time as far as we are aware, a TEM cross-section is given of crystalline bits recorded into a medium stack similar to that designed in §II. In this case however an additional intermediary DLC layer above the TiN electrode was used, which can be helpful in avoiding migration of Ti ions into the GST layer and the formation of Ti-Te compounds, as sometimes seen in PCRAM devices [35]. In addition a conventional CAFM type tip was used, of the DLC coated Si variety and with a contact diameter of approximately 50 nm.…”

The geometric effect and programming current reduction in cylindrical-shaped phase change memory

“…Phase change memories (PCMs) [1][2][3][4][5][6][7] are promising in solidstate memory technologies due to their high resistance contrast, good endurance, high-speed and low-voltage operation [8,9], and well matched Si processes and complementary metal oxide semiconductor (CMOS) technology. PCM stores data by a thermal-induced phase transition between conductive polycrystalline (set) and resistive amorphous (reset) states in a thin film of chalcogenide material.…”