Temperature dependence of soft-error rates for FF designs in 20-nm bulk planar and 16-nm bulk FinFET technologies

Zhang, H.; Jiang, Hui; Assis, T.; Ball, D. R.; Ni, Kai; Kauppila, J. S.; Schrimpf, Ronald D.; Massengill, L.W.; Bhuva, B. L.; Narasimham, B.; Hatami, Safar; Anvar, Ali; Lin, Andy; Wang, J. K.

doi:10.1109/irps.2016.7574554

Cited by 27 publications

(6 citation statements)

References 16 publications

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“…SET pulse width and feedback-loop delay of a latch are two factors that determine the overall SER of FF designs [24,25]. To a first degree, an SEU will occur only if the SET pulse width is longer than the feedback-loop delay of the latch.…”

Section: Short Set Pulsesmentioning

confidence: 99%

“…To a first degree, an SEU will occur only if the SET pulse width is longer than the feedback-loop delay of the latch. SET pulse width is strongly related to the transistor current, which varies with technology and supply voltage [24]. The presence of the delay cell in the GG-FF essentially increases the feedback-loop delay, thereby rep0utechnologies scale, the effectiveness of GG-FF is not seen to diminish.…”

Section: Short Set Pulsesmentioning

confidence: 99%

“…If inputs do not match, the output is left in floating condition (for CMOS circuits, this means the output will retain its value for a short time). Previously, researchers have used this configuration in a conventional D-latch by replacing one of the inverters by a GG with a delay cell on one of the inputs[14,[18][19][20][21][22][23][24]. For such a latch design (shown inFig.…”

mentioning

confidence: 99%

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SE Response of Guard-Gate FF in 16- and 7-nm Bulk FinFET Technologies

Cao

Bhuva

et al. 2020

IEEE Trans. Nucl. Sci.

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Section: Short Set Pulsesmentioning

confidence: 99%

Section: Short Set Pulsesmentioning

confidence: 99%

mentioning

confidence: 99%

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SE Response of Guard-Gate FF in 16- and 7-nm Bulk FinFET Technologies

Cao

Bhuva

et al. 2020

IEEE Trans. Nucl. Sci.

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“…When the temperature decreases, the delay of the transistor increases. That may cause the worst case of the SET pulse width to appear at low temperatures instead of high temperatures [6][7].…”

Section: Introductionmentioning

confidence: 99%

Research on temperature sensitivity of Single-event Transient pulse width in 28-nm bulk technology

Zhang

Liang

Fang

2021

J. Phys.: Conf. Ser.

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The influence of temperature on single-event transient (SET) pulse width has always been a hot issue in the field of anti-irradiation. Based on 3D-TCAD simulation, the temperature sensitivity of the SET pulse width of 28-nm bulk devices has been studied. The simulation results show that the electrical characteristics of the device shows an anti-temperature effect, but the worst case of SET pulse width still occurs at high temperature rather than low temperature. The influence of the triple-well structure on the temperature sensitivity of the SET pulse width has also been studied. The N+ deep well can significantly increase the SET pulse width when hitting NMOS device and enhance the temperature sensitivity of the SET pulse width. The research content of this article will provide reference for the design of radiation resistant chip.

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“…Fin shape has huge impact on the performance of FinFET [6]. Also, there are some other parameters like fin height, fin angle, doping concentration, temperature which affects the device performance [7][8][9][10][11]. Literature shows that, with increment in fin width, drive current also increases.…”

Section: Introductionmentioning

confidence: 99%

Performance Optimization of FinFET Configurations at 14 nm Technology Using ANN-PSO

Srishti¹,

Kaur²

2019

Communications in Computer and Information Science

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In this paper, device performance of 14 nm FinFETs have analyzed and electrical parameters like Ion, Ioff, Ion/Ioff, SS, DIBL and power dissipation are measured. These devices have also been analyzed in terms of V-I characteristics. Further, the effect of fin width on device performance was investigated by designing similar FinFETs with different top fin width at 14 nm technology. The designed structures have been simulated using drift diffusion model. In order to validate the results, same structures are also designed & simulated with 20 nm gate length. Also, the FinFETs' performance was optimized using ANN with the PSO algorithm. Both results i.e. optimization results and simulation results were closely matched with 0.48% error.

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Temperature dependence of soft-error rates for FF designs in 20-nm bulk planar and 16-nm bulk FinFET technologies

Cited by 27 publications

References 16 publications

SE Response of Guard-Gate FF in 16- and 7-nm Bulk FinFET Technologies

SE Response of Guard-Gate FF in 16- and 7-nm Bulk FinFET Technologies

Research on temperature sensitivity of Single-event Transient pulse width in 28-nm bulk technology

Performance Optimization of FinFET Configurations at 14 nm Technology Using ANN-PSO

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