Temperature dependence of NBTI induced delay

Abstract

Negative Bias Temperature Instability (NBTI) has become a major reliability concern for nanoscaled PMOS transistors. NBTI is a thermally activated process and its aftereffects (e.g. threshold voltage shift, current degradation and delay increment) increase exponentially with the rise in temperature. This paper presents a model of temperature impact on NBTI induced delay for PMOS transistor. It demonstrates the model on 90nm, 65nm and 45nm Predictive Technology Model (PTM) designs operating at temperature range 25-125 o C. The results show a strong correlation of NBTI induced delay with threshold voltage shift and holes mobility degradation. The key insights observed are: (a) NBTI induced threshold voltage shift is temperature sensitive and increases up to 42% at high temperatures, (b) NBTI degrades holes mobility in PMOS inversion layer and the degradation reaches 8% in 45nm technology and (c) The impact of NBTI on PMOS transistor delay becomes significant at high temperature and increases by approximately 2.5% in each successive technology reaching 11.5% in 45nm technology.

Self-impact of NBTI effect on the degradation rate of threshold voltage in PMOS transistors

“…The deep dependency of NBTI to temperature is because the diffusion sub-processes of R-D modeling framework in oxide layer follow Fick's law, (e.g., hydrogen diffusion rate (D H ) decreases linearly with decreasing H density from Si-SiO 2 interface) and temperature variation exponentially affects the diffusion rate based on Arrhenius relation, which can be written as [9]:…”

BTI impact on logical gates in nano-scale CMOS technology

“…BTI induced ∆V th of each MOS transistor has its contribution to the additional gate delay [13]. A generalized formula that relate BTI induced ∆V th in a transistor to the additional delay is given by [10]:…”

“…In recent years, there is an escalation of interest in BTI analysis at the gate level [10][11][12][13][14][15]. Paul et al in [10] pioneered the work by performing NBTI analysis for the continuous inputs that resulted in the worst degradation and Haldun et al in [11] carried out the analysis for a modified model.…”

“…Paul et al in [10] pioneered the work by performing NBTI analysis for the continuous inputs that resulted in the worst degradation and Haldun et al in [11] carried out the analysis for a modified model. Kumar et al in [12] and Khan et al in [13] presented NBTI analysis for dynamic inputs. Luo et al in [14] analyzed NBTI in the gates by considering stacking effect and Rakesh et al in [15] introduced various process and design parameters in the analysis.…”

On the Simulation of NBTI-Induced Performance Degradation Considering Arbitrary Temperature and Voltage Variations

“…Higher temperature can accelerate the generation of interface traps and thus exacerbates performance degradation. In [5], the authors showed that threshold voltage shift can increase up to 42% at high temperature. In addition to stress probability and temperature, supply voltage is also a major factor contributing to NBTI degradation.…”