Temperature dependence of MOSFET characteristics in weak inversion

Nishida, M.; Ohyabu, H.

doi:10.1109/t-ed.1977.18987

Cited by 14 publications

(2 citation statements)

References 15 publications

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“…In this region, drain current has an exponential relationship with threshold voltage [8] making the impact of global n-to-p mismatch more prominent. Moreover, the current-temperature relationship in weak inversion is opposite to that in strong inversion [9]. In strong inversion drain current is made up of drift current while in weak inversion it is made up of diffusion current.…”

Section: Experimental Methodologymentioning

confidence: 91%

Pulse width degradation in 45nm ASIC design due to global and environmental variations

Chawla

Marchal

Amara

et al. 2009

2009 International Conference on Microelectronics - ICM

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Global and Environmental variations together are responsible for differences in timing from one die to another for an ASIC design. The tried and tested method of corners and margins is still the dominant method in ASIC industry to assure the timing characteristics of a design. However, the increasing margins limit the scaling of maximum achievable frequency for a given die size, especially because of minimum pulse width violation. The importance of clock tree pulse-width variations due to global N-to-P mismatch is increasing with decreasing pulse width. To continue scaling the clock frequency, we may need to make application specific margins and corners. In this work, we have estimated the impact of pulse width variations on standard cells in a clock library using industrial models and spice simulations. We found that by unbalancing the first stage of a cell with respect to rise and fall edge in a multiple supply voltage design, we could halve the pulse width variations with minimal effect on delay and slew.Index Terms-Clock tree pulse width, global N-to-P mismatch

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Section: Experimental Methodologymentioning

confidence: 91%

Pulse width degradation in 45nm ASIC design due to global and environmental variations

Chawla

Marchal

Amara

et al. 2009

2009 International Conference on Microelectronics - ICM

View full text Add to dashboard Cite

show abstract

“…In this region, drain current begins to flow when the bulk Fenni potential is greater than twice of the surface potential at the end of the channel [14]. The current has an exponential dependence on the gate-to-source voltage of an MOSFET [15].…”

Section: A Subthreshold Operationmentioning

confidence: 99%

A novel 2-terminal zener voltage reference

Kok

Siek

2011

2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS)

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In this paper, we present a novel 2-terminal zener voltage reference of 0.23V which is also commonly known as a shunt regulator. The circuit realizes the use of sub-threshold technology of MOSFET and it is simulated with Chartered O.lS"m CMOS process. Simulation results explicitly show that a stable 2-terminal zener voltage reference of 0.23V is generated with a temperature coefficient of 3.7ppm/oC across a temperature range of 0 to 150°C. Furthermore, the minimum operating current is 10JLA which yields a low power consumption of 2.3"W. The line regulation is 22.SmVN. This circuit only consumes a silicon area of 0.0009 mm 1 • Being 2-terminal, this simple design can be used to provide a very low and stable voltage difference between any two nodes in a circuit.

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Bauformen des MOSFET

Paul¹

1994

MOS-Feldeffekttransistoren

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Temperature dependence of MOSFET characteristics in weak inversion

Cited by 14 publications

References 15 publications

Pulse width degradation in 45nm ASIC design due to global and environmental variations

Pulse width degradation in 45nm ASIC design due to global and environmental variations

A novel 2-terminal zener voltage reference

Bauformen des MOSFET

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