Temperature dependence of DC transport characteristics for a two-dimensional electron gas in an undoped Si/SiGe heterostructure

Abstract

We investigate DC characteristics of a two-dimensional electron gas (2DEG) in an undoped Si/SiGe heterostructure and its temperature dependence. An insulated-gate field-effect transistor was fabricated, and transfer characteristics were measured at 4 K–300 K. At low temperatures (T < 45 K), source electrons are injected into the buried 2DEG channel first and drain current increases with the gate voltage. By increasing the gate voltage further, the current saturates followed by a negative transconductance observed, which can be attributed to electron tunneling from the buried channel to the surface channel. Finally, the drain current is saturated again at large gate biases due to parallel conduction of buried and surface channels. By increasing the temperature, an abrupt increase in threshold voltage is observed at T ∼ 45 K and it is speculated that negatively charged impurities at the Al2O3/Si interface are responsible for the threshold voltage shift. At T > 45 K, the current saturation and negative transconductance disappear and the device acts as a normal transistor.

Cryogenic Si/SiGe Heterostructure Flash Memory Devices

“…To investigate the window of operational temperatures, we performed the retention tests up to 80 K. The memory window is defined as the difference of the threshold voltages for two states and is larger than 1.4 V for the retention time of 10 4 seconds at temperatures lower than 40 K. At T = 60 K, the window shrinks from 0.35 V and almost disappears with a retention time of 10 3 seconds. At higher temperatures, the window is completely closed, since the surface channel dominates the current transport in this bilayer system. , The surface tunneling rates of the carriers in the buried channel become very small, so only one charge state exists, and the memory window is eliminated. To further extend the range of operation temperatures, the surface channel must be insulating at higher temperatures to keep the device at nonequilibrium.…”

“…By performing a backward scan of gate biases (regime (iv) in Figure d), the device is turned off at a larger threshold voltage (∼1.8 V). The peculiar I – V characteristics are attributed to the surface tunneling and have been explained in detail in prior works. − Here, we briefly review the operational principles of the Si/SiGe heterostructure FET before we demonstrate its memory characteristics. First, the current increases with the gate bias as a conventional transistor ((i) in Figures d and ).…”

“…Since the mobility in the Si cap layer is much lower than that in the buried QW, the effective conductance of this bilayer system becomes smaller, and the current is reduced with the gate bias. Then, the current is saturated again under a higher gate bias, since the conductivity in the buried channel is pinned by effective screening of the surface channel. , While increasing the gate bias induces more carriers into the Si cap layer, its conductivity is much lower than that in the buried channel, leading to the current saturation. Once the gate voltage is swept back from 2.0 V, the current starts to decrease (regime (iv) in Figure d).…”

“…For the reverse scan, carriers accumulate in the Si cap layer by the surface tunneling from the buried channel. Since the effective capacitance for the surface channel is larger than that for the buried channel, it requires a smaller potential drop to deplete the carriers for the reverse scan, leading to a higher turn-off voltage …”

“…For large-scale qubit control and readout, complementary metal-oxide-semiconductor (CMOS) logic and memory devices at cryogenic temperatures are required to solve issues of signal latency, thermal noise, and wiring complexity. , Recently, quite a few works on cryo-CMOS logic devices have been demonstrated, − but only a few memory devices were demonstrated at cryogenic temperatures (∼77 K), such as static random access memory (SRAM), , dynamic random access memory (DRAM), , and flash memories. − Furthermore, most cryogenic logic and memory devices were fabricated on the Si MOS platform. While prior works on the Si/SiGe heterostructure logic devices − were presented, Si/SiGe memory devices have not been demonstrated yet. In this work, we demonstrate a cryogenic flash memory device on the undoped Si/SiGe heterostructure.…”