Temperature Dependence and Temperature-Aware Sensing in Ferroelectric FET

Gupta, Aniket; Ni, Kai; Prakash, Om; Hu, Xiaobo Sharon; Amrouch, Hussam

doi:10.1109/irps45951.2020.9129226

Cited by 39 publications

(14 citation statements)

References 13 publications

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“…The range of temperature-induced degradation is aligned with presented measurement data in literature such as [30], [31]. In this work, we have relied on our previous work where we studied the impact of temperature on FeFET devices [20]. The impact of temperature increase on the P r (remnant polarization), P s (saturation polarisation), and E c (coercive field) have been extracted from measured Q F E -V F E hysteresis loop at different temperatures [30].…”

Section: Our Fefet Bit Error Modelsupporting

confidence: 71%

“…Content may change prior to final publication. [20]. is additionally deposited on top of the oxide layer.…”

Section: Overview Of Fefet Technologymentioning

confidence: 99%

“…3: Temperature impact on the memory window of FeFET. A higher temperature impact more considerably the high-V th curve that represents logic '0' than low-V th curve that represents logic '1' [20].…”

Section: Low-vth Curvementioning

confidence: 99%

“…Note that temperature effects have been measured from fabricated devices and then modeled inside our built TCADbased FeFET. Please refer to [24], [25] for further details on the device calibration and measurements.…”

Section: Low-vth Curvementioning

confidence: 99%

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FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors

Yayla

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Gupta

et al. 2022

IEEE Trans. Comput.

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Ferroelectric FET (FeFET) is a highly promising emerging non-volatile memory (NVM) technology, especially for binarized neural network (BNN) inference on the low-power edge. The reliability of such devices, however, inherently depends on temperature. Hence, changes in temperature during run time manifest themselves as changes in bit error rates. In this work, we reveal the temperature-dependent bit error model of FeFET memories, evaluate its effect on BNN accuracy, and propose countermeasures. We begin on the transistor level and accurately model the impact of temperature on bit error rates of FeFET. This analysis reveals temperature-dependent asymmetric bit error rates. Afterwards, on the application level, we evaluate the impact of the temperature-dependent bit errors on the accuracy of BNNs. Under such bit errors, the BNN accuracy drops to unacceptable levels when no countermeasures are employed. We propose two countermeasures: (1) Training BNNs for bit error tolerance by injecting bit flips into the BNN data, and (2) applying a bit error rate assignment algorithm (BERA) which operates in a layer-wise manner and does not inject bit flips during training. In experiments, the BNNs, to which the countermeasures are applied to, effectively tolerate temperature-dependent bit errors for the entire range of operating temperature.

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Section: Our Fefet Bit Error Modelsupporting

confidence: 71%

“…Content may change prior to final publication. [20]. is additionally deposited on top of the oxide layer.…”

Section: Overview Of Fefet Technologymentioning

confidence: 99%

Section: Low-vth Curvementioning

confidence: 99%

Section: Low-vth Curvementioning

confidence: 99%

See 2 more Smart Citations

FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors

Yayla

Buschjäger

Gupta

et al. 2022

IEEE Trans. Comput.

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“…As a result, the multi-domain FE model reproduces qualitatively the experimentally observed binary and multi-level properties of Fe-FinFET. The ferroelectric specific parameters have been calibrated against measurements of a ferroelectric capacitor Gupta et al (2020). Not considered in this work are the variation sources introduced by the FE layer itself (saturation polarization, remnant polarization, and coercive field), resulting in a more optimistic analysis Ni et al (2020).…”

Section: Process Variation Effects and Error Probability Modelingmentioning

confidence: 99%

All-in-Memory Brain-Inspired Computing Using FeFET Synapses

et al. 2022

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The separation of computing units and memory in the computer architecture mandates energy-intensive data transfers creating the von Neumann bottleneck. This bottleneck is exposed at the application level by the steady growth of IoT and data-centric deep learning algorithms demanding extraordinary throughput. On the hardware level, analog Processing-in-Memory (PiM) schemes are used to build platforms that eliminate the compute-memory gap to overcome the von Neumann bottleneck. PiM can be efficiently implemented with ferroelectric transistors (FeFET), an emerging non-volatile memory technology. However, PiM and FeFET are heavily impacted by process variation, especially in sub 14 nm technology nodes, reducing the reliability and thus inducing errors. Brain-inspired Hyperdimensional Computing (HDC) is robust against such errors. Further, it is able to learn from very little data cutting energy-intensive transfers. Hence, HDC, in combination with PiM, tackles the von Neumann bottleneck at both levels. Nevertheless, the analog nature of PiM schemes necessitates the conversion of results to digital, which is often not considered. Yet, the conversion introduces large overheads and diminishes the PiM efficiency. In this paper, we propose an all-in-memory scheme performing computation and conversion at once, utilizing programmable FeFET synapses to build the comparator used for the conversion. Our experimental setup is first calibrated against Intel 14 nm FinFET technology for both transistor electrical characteristics and variability. Then, a physics-based model of ferroelectric is included to realize the Fe-FinFETs. Using this setup, we analyze the circuit’s susceptibility to process variation, derive a comprehensive error probability model, and inject it into the inference algorithm of HDC. The robustness of HDC against noise and errors is able to withstand the high error probabilities with a loss of merely 0.3% inference accuracy.

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