Temperature based performance analysis of doping-less tunnel field effect transistor

Yadav, Dharmendra Singh; Sharma, Dheeraj; Agrawal, Rahul; Prajapati, Gaurav; Tirkey, Sukeshni; Raad, Bhagwan Ram; Bajaj, Varun

doi:10.1109/icomicon.2017.8279131

Cited by 13 publications

(2 citation statements)

References 17 publications

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“…For this BTBT, SRH and TAT models a.e. considered with deviation in Temp K [21,22]. The OFF-state conditions of proposed device are much precious circuit-level applications because I on /I off ratio is highly affected.…”

Section: Impact Of Temperature and Itcs On Analog/rf Parametersmentioning

confidence: 99%

Assessment of temperature and ITCs on single gate L-shaped tunnel FET for low power high frequency application

Singh,

Yadav

2024

Eng. Res. Express

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In vertical TFET structure, controllability over the gate is enhanced because of the favorable electrostatic potential and tunneling under the entire gate region by preventing the direct source to drain tunneling. For an L-shaped TFET, the Band-to-band-tunneling (BTBT) is perpendicular and parallel to the channel length. Also, it has a higher Ion (ON-current) with suppressed ambipolar current (low Iambi) and is more scalable than other vertical BTBT mechanism-based TFET structures. The reliability of n-type single gate L-shaped TFET (SG-nLTFET) is investigated by examining: (1) impact of temperature variation (from 260K to 460K) and (2) Interface trap charge (ITCs) polarity at ﬁxed charge density on analog /RF /linearity ﬁgure of merits (FOMs). The obtained results reveal that change in polarity of ITCs at the Si/HfO2interface, modify the analogue characteristics of the SG-nLTFET signiﬁcantly in terms of turn-on voltage as well as Ion. The temperature sensitivity of SG-nLTFET device indicates that the Shockley–Read–Hall (SRH) and Trap-Assisted-Tunneling (TAT) phenomenon dominates at lower gate bias and degrades the Ion/Ioff ratio at high temperatures. On the other hand, the BTBT mechanism predominates in the subthreshold regime of transfer characteristics. Furthermore, the results reveal that the oﬀ-state current (Ioff) degrades dramatically at high temperatures. According to the empirical analysis, SG-nLTFET is insusceptible to Positive-ITCs (Donor trap charges, P-ITCs) present at Si/HfO2interface in comparison to Negative-ITCs (Acceptor trap charges, N-ITCs).

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Section: Impact Of Temperature and Itcs On Analog/rf Parametersmentioning

confidence: 99%

Assessment of temperature and ITCs on single gate L-shaped tunnel FET for low power high frequency application

Singh,

Yadav

2024

Eng. Res. Express

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“…11(b), due to the fact that the gate-drain underlap structure increases the distance between the gate and drain regions, weakens the capacitive coupling, and reduces the effective charge concentration in the uncovered region of the gate. [41,42] 0 0.25 0.50 0.75 1.00 1. 25 Gate voltage, V gs (V) Gate voltage, V gs (V) The cut-off frequency is the frequency at which the current gain becomes unity, and plays a significant role in deciding the device performance at high frequency, [43] as shown below:…”

Section: Analog/rf Characteristics Analysismentioning

confidence: 99%

Ambipolar performance improvement of the C-shaped pocket TFET with dual metal gate and gate–drain underlap

Zhao¹,

Chen²,

Liu³

et al. 2023

Chinese Phys. B

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In this paper, dual-metal gate and gate-drain underlap designs are introduced to reduce the ambipolar current of the device based on the C-shaped pocket TFET(CSP-TFET). The effects of gate work function and gate-drain underlap length on the DC characteristics and analog/RF performance of CSP-TFET devices, such as on-state current (I on), ambipolar current (I amb), transconductance (g m), cut-off frequency (f T) and gain-bandwidth product (GBP) are analyzed and compared in this work. And a combination of both the dual-metal gate and gate-drain underlap designs has been proposed for the C-shaped pocket dual metal underlap TFET (CSP-DMUN-TFET), which contains a C-shaped pocket area that significantly increases the on-state current of the device, and this combination design substantially reduces the ambipolar current. The results show that the CSP-DMUN-TFET has excellent performance, including high I on (9.03×10-4 A/μm), high I on/I off (~1011), low SS avg (~13 mV/dec), low I amb (2.15×10-17 A/μm). The CSP-DMUN-TFET has the capability to fully suppress ambipolar currents while maintaining high on-state currents, making it a potential replacement for next generation of semiconductor devices.

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Analysis of Channel Doping Variation on Transfer Characteristics to High Frequency Performance of F‐TFET

Singh,

Yadav

2023

Advanced Ultra Low‐Power Semiconductor Devices

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Temperature based performance analysis of doping-less tunnel field effect transistor

Cited by 13 publications

References 17 publications

Assessment of temperature and ITCs on single gate L-shaped tunnel FET for low power high frequency application

Assessment of temperature and ITCs on single gate L-shaped tunnel FET for low power high frequency application

Ambipolar performance improvement of the C-shaped pocket TFET with dual metal gate and gate–drain underlap

Analysis of Channel Doping Variation on Transfer Characteristics to High Frequency Performance of F‐TFET

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