Temperature-Aware Placement for SOCs

Tsai, Jeng-Liang; Chen, C.C.-P.; Chen, Guoqiang; Goplen, B.; Qian, Haifeng; Zhan, Yinwei; Kang, Sung‐Mo; Wong, D.F.; Sapatnekar, Sachin S.

doi:10.1109/jproc.2006.879804

Cited by 43 publications

(6 citation statements)

References 37 publications

(41 reference statements)

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“…Optimizing placement in cell-based designs generally involves minimizing the area of cells and the power consumption due to wire capacitance. Thermalaware floorplanning methods for VLSI have been proposed [3,4,5,6,7,8,9]. Thermal-aware 3D network-on-chip (NoC) designs have been proposed [10,11].…”

Section: Introductionmentioning

confidence: 99%

Thermal placement on PCB of components including 3D ICs

Satomi

Hachiya

Kanamoto

et al. 2020

IEICE Electron. Express

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In this letter, we propose a method for optimizing the thermal placement of heat and non-heat generating electronic components on a printed circuit board (PCB). Use a genetic algorithm to optimize the maximum temperature of the PCB and the total wire length between components. In the case that chips stacked in 3D ICs are reconfigurable, each chip construction of 3D ICs is also changed simultaneously. The temperature of each component is obtained by circuit simulation using a simple thermal circuit model. The experimental results demonstrate that the placement of components can be optimized well for lowering the maximum temperature with shorter wire lengths.

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Section: Introductionmentioning

confidence: 99%

Thermal placement on PCB of components including 3D ICs

Satomi

Hachiya

Kanamoto

et al. 2020

IEICE Electron. Express

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“…It is very important to keep the thermal resistance at bay as this may increase the package cost and the overall cost of the product. Observation of the thermal contours of certain industrial chip shows that the temperature at the hotspots can exceed 100°C (Tsai et al, 2006).…”

Section: Introductionmentioning

confidence: 99%

Exploration of Temperature-Aware Placement Approaches in 2D and 3D Stacked Systems

Vaddina

Liljeberg

Plosila

2013

International Journal of Adaptive, Resilient and Autonomic Systems

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Technology scaling has brought about dramatic rises in the on-chip power density of modern microprocessors. This has led to greater scrutiny and awareness of thermal management techniques which allows to uphold the thermal integrity of the chip. Higher temperatures or uneven distribution of temperatures result in timing uncertainties which induces performance and reliability concerns for the system. Future thermal problems would include 3D circuits. Three-dimensional technology offers greater device integration, reduced signal delay and reduced interconnect power. It also provides greater design flexibility by allowing heterogeneous integration. However, 3D technology also exacerbates the on-chip thermal issues and increases packaging and cooling costs. In order to resolve these issues, and avoid high and uneven temperatures, accurate thermal modeling and analysis, and thermal-aware placement optimizations are essential before tapeout. This paper presents an exploration of temperature-aware placement approaches in both the 2D and 3D stacked systems. Various thermal models were developed to investigate the effect of uniform power distribution, thermal-aware placement in 2D chips and 3D stacked systems on the thermal performance of the system thereby providing with metrics which can be used for thermal-aware mapping.

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“…For instance, power devices can remain within their safe operating area [1] or failures in ICs can be reduced (e.g. logic errors when reading data) [2] thanks to an optimal thermal management and smart protection strategies. However, abnormal events are usually produced at very short time scales (microsecond range), in which the heat removal system cannot immediately cool down a local temperature peak produced inside the die.…”

Section: Introductionmentioning

confidence: 99%

“…These facts have suggested the development and improvement of thermal management strategies at the chip level. Although they are usually conceived by following numerical simulation [1,2,4], they should be experimentally corroborated. Therefore, temperature measurement is an imperative requirement to really improve the modelling results and to check the final thermal performances of the chip itself.…”

Section: Introductionmentioning

confidence: 99%

Steady-state sinusoidal thermal characterization at chip level by internal infrared-laser deflection

Perpiñà¹,

Jordà²,

Vellvehı́³

et al. 2008

J. Phys. D: Appl. Phys.

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A new approach is reported for thermally characterizing microelectronic devices and integrated circuits under a steady-state sinusoidal regime by internal infrared-laser deflection (IIR-LD). It consists of extracting the amplitude and phase Bode plots of the temperature profile inside the chip (depth-resolved measurements in the frequency domain). As a consequence, not only are the IIR-LD performances significantly improved (accuracy, robustness to noise, control of boundary conditions and heat flux confinement) but also the direct temperature measurement is feasible when thin regions are inspected and thermal parameters can be easily extracted (thermal diffusivity). In order to show the efficiency of this technique, a thermal test chip (TTC) is used. The TTC is thermally excited by imposing a cosine-like voltage waveform. As a result, a vertical temperature profile inside the die is obtained depending on the heating frequency. Repeating this procedure at several frequencies, the frequency response of the chip internal temperature profile is derived. By comparing the experimental results with the model predictions, good agreement is achieved. This technique allows evaluation of the thermal behaviour at the chip level; also it could be useful for failure analysis.

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Temperature-Aware Placement for SOCs

Cited by 43 publications

References 37 publications

Thermal placement on PCB of components including 3D ICs

Thermal placement on PCB of components including 3D ICs

Exploration of Temperature-Aware Placement Approaches in 2D and 3D Stacked Systems

Steady-state sinusoidal thermal characterization at chip level by internal infrared-laser deflection

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