Temperature-aware global placement

Obermeier, Bernd; Johannes, Frank

doi:10.1109/aspdac.2004.1337555

Cited by 35 publications

(27 citation statements)

References 10 publications

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“…Hung et al [12] have used floorplanning with genetic algorithms to reduce the peak temperatures and optimize area. Reduction of clock tree power using activity based register clustering and thermal aware placement has been proposed by Cheon et al [13] and Obermeier et al [14]. All of the above works have focused primarily on reducing peak temperatures.…”

Section: Related Workmentioning

confidence: 99%

Floorplan driven leakage power aware IP-based SoC design space exploration

Gupta

Dutt

Kurdahi

et al. 2006

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis

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Multi-million gate System-on-Chip (SoC) designs increasingly rely on Intellectual Property (IP) blocks. However, due to technology scaling the leakage power consumption of the IP blocks has risen thus leading to possible thermal runaway. In IP-based design there has been a disconnect between system level design and physical level steps such as floorplanning which can lead to failures in manufactured chips. This necessitates coupling between system level and physical level design steps. The leakage power of an IP-block increases with its temperature which is dependent on the SoC's floorplan due to thermal diffusion. We have observed that different floorplans of the same SoC can have up to 3X difference in leakage power. Hence the system designer needs to be aware of this design space between floorplans and leakage power. We propose a leakage aware exploration (LAX) framework which enables the system designer to create this design space early in the design cycle and provides an opportunity to make changes in the system design. We show the size of the design space generated by applying LAX on ten industrial SoC designs from Freescale Semiconductor Inc. and observe that the leakage power can vary by as much as 190% for 65% difference in the inactive area.

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Section: Related Workmentioning

confidence: 99%

Floorplan driven leakage power aware IP-based SoC design space exploration

Gupta

Dutt

Kurdahi

et al. 2006

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis

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“…There are several placers which attempt to spread out highly-switching cells across the chip [4] [13]. In our experiments we use the publicly available academic placer Dragon [18], which does not have the capability of spreading the frequently switching cells.…”

Section: Correcting Step: Gate-sizing For Power Noise and Timingmentioning

confidence: 99%

“…In [19], the authors observe that an effective way to allocate decaps is to distribute them to all grid nodes, assigning more decaps to grid nodes of the blocks with high switching rates. Some previous works [4] [13] propose to reduce power noise by spreading the frequently switching cells evenly across the chip to eliminate hot spots. In [4], the authors include thermal cost function in a partition-based placer.…”

Section: Introductionmentioning

confidence: 99%

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Timing-Aware Power-Noise Reduction in Placement

Yeh

Merek-Sadowska

2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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In this paper, we describe a placement-level decap insertion technique whose objective is to reduce power-noise, taking into account circuit timing. Our approach consists of prediction and correction steps. Before placement, we estimate the power noise of each cell considering switching frequency of cells which, after placement, will most likely be in the neighborhood. If a frequently switching cell has neighbors that switch infrequently, it is unlikely that this cell will suffer from a power noise problem. Based on the cell power noise estimation, we add decap padding to each cell. Then we invoke a standard cell placement tool and perform power grid analysis. We eliminate the power grid noise by gate sizing. Our technique can allocate decaps to improve power noise, power consumption, and timing. We propose two gate-sizing algorithms. The first one uses a Sequence of Linear Programs (SLP) formulation, and the second one uses a budgeting-based heuristic algorithm. The SLP algorithm can produce better power noise results than the heuristic, at the expense of run time. Experimental results show that our techniques can effectively reduce power noise and still meet timing constraints.

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“…The Poisson equation can be solved efficiently by a geometric multigrid solver [27], [20]. If chip's charge density D Chip is constant then module density d is exactly charge density D plus D Chip [12].…”

Section: Move Forcementioning

confidence: 99%

Fast and robust quadratic placement combined with an exact linear net model

Spindler¹,

Johannes²

2006

Proceedings of the 2006 IEEE/ACM International Conference on Computer-Aided Design - ICCAD '06

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Abstract-This paper presents a robust quadratic placement approach, which offers both high-quality placements and excellent computational efficiency. The additional force which distributes the modules on the chip in force-directed quadratic placement is separated into two forces: hold force and move force. Both of these forces are determined without any heuristics. Based on this novel systematic force implementation, we show that our iterative placement algorithm converges to an overlapfree placement. In addition, engineering change order (ECO) is efficiently supported by our placer. To handle the important trade-off between CPU time and placement quality, a deterministic quality control is presented.In addition, a new linear net model is proposed, which accurately models the half-perimeter wirelength (HPWL) in the quadratic cost function of quadratic placement. HPWL in general is a linear metric for netlength and represents an efficient and common estimation for routed wirelength. Compared with the classical clique net model, our linear net model reduces memory usage by 75%, CPU time by 23% and netlength by 8%, which is measured by the HPWL of all nets.Using the ISPD-2005 benchmark suite for comparison, our placer combined with the new linear net model has just 5.9% higher netlength but is 16× faster than APlace, which offers the best netlength in this benchmark. Compared to Capo, our placer has 9.2% lower netlength and is 5.4× faster.In the recent ISPD-2006 placement contest, in which quality is mainly determined by netlength and CPU time, our placer together with the new net model produced excellent results.

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Temperature-aware global placement

Cited by 35 publications

References 10 publications

Floorplan driven leakage power aware IP-based SoC design space exploration

Floorplan driven leakage power aware IP-based SoC design space exploration

Timing-Aware Power-Noise Reduction in Placement

Fast and robust quadratic placement combined with an exact linear net model

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