Temperature-Aware DRAM Cache Management—Relaxing Thermal Constraints in 3-D Systems

Zhou, Minxuan; Prodromou, Andreas; Wang, Rui; Yang, Hailong; Qian, Depei; Tullsen, Dean M.

doi:10.1109/tcad.2019.2927528

Cited by 4 publications

(2 citation statements)

References 56 publications

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“…基于硅穿孔 (through silicon via, TSV) 技术的 3D 封装存储器 (high-bandwidth memory/high-bandwidth memory 2, HBM/HBM2) 是目前最实际的缩短存储器和处理器之间距离的手段, 由于互连线短且数量多, 存储器的带宽和时延都可以得到大大改善. 需要解决的问题是如何降低功耗减少发热, 如何设计有效的散热机制, 以及如何管控存储器物理空间的访问, 避免局部过热 [32] .…”

Section: 面临的挑战unclassified

Key issues in exascale computing

Qian¹,

Wang²

2020

Sci. Sin.-Inf.

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Over the past several decades, high performance computing (HPC) in China has undergone tremendous growth under the continuous support of national research programs. The development of exascale computers is the current goal set by the National Key R&D Project on HPC. Starting with a brief historical review of China's HPC development, this article analyzes the major challenges encountered in developing exascale computers. Thereafter, some important issues in realizing exascale computing are discussed, including architecture, processor, interconnect, parallel system software, parallel programming, algorithm, and resilience.

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Section: 面临的挑战unclassified

Key issues in exascale computing

Qian¹,

Wang²

2020

Sci. Sin.-Inf.

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“…Many previous studies have proposed different methods for reducing retention errors. Three main categories used to mitigate DRAM retention errors are the bit repair methods [13][14][15][16], error correction code-based (ECC-based) mitigation techniques [17,18], and temperature-aware refresh (TAR) [19,20]. TAR is a method of changing the refresh interval chosen for each stack die or DRAM bank depending on the temperature during DRAM operations.…”

Section: Introductionmentioning

confidence: 99%

Temperature Estimation of HBM2 Channels with Tail Distribution of Retention Errors in FPGA-HBM2 Platform

et al. 2022

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High-bandwidth memory 2 (HBM2) vertically stacks multiple dynamic random-access memory (DRAM) dies to achieve a small form factor and high capacity. However, it is difficult to diagnose HBM2 issues owing to their structural complexity and 2.5D integration with heterogeneous chips. The effects of the temperature at the base logic die (TL), and the refresh interval at the stacked DRAM dies, were experimentally investigated by counting the dynamic retention errors in the eight channels in an HBM2. TL was indirectly controlled by the heatsink temperature (TS). The lognormal distribution represents the distribution of the cell counts with varying refresh times. All Z-magnitudes (multiples of the distribution standard deviation) over the various refresh cycle times (RCTs) up to 2.045 s in a single channel at TL of 70 °C appeared below 4.4, which means that the error bits belong to the tail distribution. The Z-differences in the eight channels were distinctively larger than the Z-differences of the same channels at a constant temperature, demonstrating that the temperature difference in the stacked dies resulted in larger Z-differences. The largest Z-difference was 0.091 for all the channels at an RCT of 1.406 s, which was approximately 4.82 times smaller than the Z-difference between the TL temperatures of 70 °C and 80 °C in a single channel. The Z-difference between the TL temperatures of 70 °C and 72 °C in a single channel was approximately the same as the Z-difference in all the channels at an RCT of 2.045 s.

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Ultra Efficient Acceleration for De Novo Genome Assembly via Near-Memory Computing

Zhou

et al. 2021

2021 30th International Conference on Parallel Architectures and Compilation Techniques (PACT)

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Temperature-Aware DRAM Cache Management—Relaxing Thermal Constraints in 3-D Systems

Cited by 4 publications

References 56 publications

Key issues in exascale computing

Key issues in exascale computing

Temperature Estimation of HBM2 Channels with Tail Distribution of Retention Errors in FPGA-HBM2 Platform

Ultra Efficient Acceleration for De Novo Genome Assembly via Near-Memory Computing

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