Tem Analysis of Failed Bits and Improvement of Data Retention Properties in Megabit-Drams

Onishi, S.; Ayukawa, A.; Tanaka, Kenichi; Sakiyama, K.

doi:10.1109/irps.1990.363531

Cited by 3 publications

(3 citation statements)

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“…SPER involves the process of recrystallizing an implantation-induced amorphous layer by annealing the layer at temperatures above 500°C. 3,4 The effect of strain on many factors in the study of semiconductors has been very important throughout the years in an effort to help continue the scaling of complementary metal-oxide semiconductor ͑CMOS͒ devices. In unpatterned wafers, the regrowth is unidirectional toward the surface.…”

Section: Introductionmentioning

confidence: 99%

Effect of stress on the evolution of mask-edge defects in ion-implanted silicon

Olson

Kuryliw

Jones

et al. 2006

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

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Section: Introductionmentioning

confidence: 99%

Effect of stress on the evolution of mask-edge defects in ion-implanted silicon

Olson

Kuryliw

Jones

et al. 2006

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

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“…I and 2). Gate edge line defects, originating in S/D regions and protruding under sidewall oxide, resemble defects reported to be responsible for electrical leakage and single bit failures (1)(2)(3)(4)(5). Gate edge defects are approximately 3 to 5• more numerous in B-implanted regions than in As-implanted regions.…”

Section: Resultsmentioning

confidence: 87%

Effect of Device Processing Conditions on Extended Dislocations and Defects in Ti‐Salicided Source/Drain Regions of Silicon Integrated Circuits

Guldi

1993

J. Electrochem. Soc.

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The propagation of incipient n+ and p+ source/drain (S/D) implant damage into extended dislocations at gate and field edges was studied for a variety of different processing conditions used to fabricate typical Ti‐salicided complimentory metal oxide semiconductor transistors. Gate edge dislocations were observed predominantly in n‐wells, while field edge defects occurred in both n and p‐wells. Both gate edge and field edge dislocations were found to be strongly affected by stresses from field oxide edges and overlying dielectric spacer layers. The use of a low‐stress polysilicon‐to‐metal dielectric is effective in reducing the density of extended dislocations in both n‐ and p‐wells. Moderation of field oxide edge stress, either by reducing the field oxide thickness or by tapering the field to active area transition region, is also effective in reducing dislocation density in the n‐well.

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“…3'5 These defects cannot be eliminated at temperatures up to 1000~ (higher temperatures would lead to an intolerable shift of the dopant profile). 9 Less steep mask sidewalls cause smoother a/c-interfaces below the mask edge and hence avoid defect formation 3'9 but are in conflict with the trend of shrinking device dimensions. A promising new way to avoid mask edge defect formation is the concept of a disposable spacer which is removed before annealing.…”

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confidence: 99%

Implantation Defects Below Mask Edges in Silicon: Structure and Effect on Devices

Cerva

Bergholz

1993

J. Electrochem. Soc.

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High-dose As + implantation and subsequent annealing produces defects just below the edge of oxide spacers or field oxide masks. They have been identified to be vacancy-type halGloop dislocations with Burgers vectors 1/3 <111> by transmission electron microscopy (TEM). Optical emission microscopy was used to localize sites with increased leakage current in n § structures. Precision plan view thinning for TEM investigation was employed to show that not the dislocation loops but nickel precipitates were responsible for the leakage. The nickel precipitated in the strain field of the mask edge and the defects. Moreover~ it is evident that mask edge defects act as nucleation centers for glide dislocations which are generated by the high stress of film edges exerted on the substrate.Ion implantation is a method to dope well-defined and small areas in ultra and very large scale integrated (U/VLSI) silicon devices. The fabrication of n+-doped regions by As + implantation entails steep dopant profiles which are welcome for shallow junction formation. The high doses needed to ensure low sheet resistances result in an amorphization of the silicon in a zone near the surface. Subsequent annealing to crystallize the amorphous layer and activate the dopants leads to defect formation usually just below the original amorphous/crystalline (a/e)-interface [end of range (EOR) defects] and at the position of the projected range Rp of the implanted ions.

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Tem Analysis of Failed Bits and Improvement of Data Retention Properties in Megabit-Drams

Cited by 3 publications

References 0 publications

Effect of stress on the evolution of mask-edge defects in ion-implanted silicon

Effect of stress on the evolution of mask-edge defects in ion-implanted silicon

Effect of Device Processing Conditions on Extended Dislocations and Defects in Ti‐Salicided Source/Drain Regions of Silicon Integrated Circuits

Implantation Defects Below Mask Edges in Silicon: Structure and Effect on Devices

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