Technology scaling effects on multipliers

Altwaijry, Hesham; Flynn, Michael J.

doi:10.1109/12.736430

Cited by 21 publications

(9 citation statements)

References 12 publications

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“…With the advent of deep-sub-micron technology, the interconnect delay dominates the performance of the multiplier [1] . Therefore conventional multiplier design approaches based on the gate delay model become less effective.…”

Section: Introductionmentioning

confidence: 99%

Integrated algorithmic logical and physical design of integer multiplier

Zhou

Yao

Liu

et al. 2005

Proceedings of the 2005 Conference on Asia South Pacific Design Automation - ASP-DAC '05

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This paper presents an integrated methodology for high-performance integer multiplier design, which combines algorithmic partial product generation, logic synthesis, and physical layout into a unified process. The interconnect delay, which dominates the performance of a multiplier, is thoroughly considered in this integration. The special structures in the multiplier are utilized to reduce the high complexity of the holistic approach. Compared with multipliers generated by a state-of-the-art tool, the timing improvements of our results are 11% for a 16-bit multiplier, and 7.5% for a 32-bit multiplier. An integrated methodology:The proposed flow integrates the algorithmic, logical and physical optimization. The tight integration allows accurate evaluation even in the high-level design stages, which improves the effectiveness of the operation. • • • • • • Hybrid non-Booth/Booth Radix-4 encoding:We develop an algorithmic approach to pick the encoded and unencoded length for the hybrid encoding. The produced encoding combines the area and timing advantage of Booth and non-Booth algorithms.

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Section: Introductionmentioning

confidence: 99%

Integrated algorithmic logical and physical design of integer multiplier

Zhou

Yao

Liu

et al. 2005

Proceedings of the 2005 Conference on Asia South Pacific Design Automation - ASP-DAC '05

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“…That is, we will compute C J (n) wholly within the RNS. n is represented as (5,8,3,4,14,17) by this set of moduli. First, compute C J (n) moduli 7, 17, and 23, and C K (n) moduli 11, 13, and 19 using (15) and (17):…”

Section: Rns Scaling Methodsmentioning

confidence: 99%

“…The values of M i * -1 are {6, 1, 2, 12, 2, 2}, as before. In the RNS, n is represented by (2,5,12,1,15,18). First, compute C J (n) moduli 7, 17, and 23, and C K (n) moduli 11, 13, and 19 using (15) and (17):…”

Section: Worked Example Of Unambiguous Scaling Methodsmentioning

confidence: 99%

“…Finally, add ∆C(n) to the C K (n) values to obtain the remaining scaled moduli: C J (n) mod 11 = C K (n) + ∆C(n) mod 11 = 5+8 mod 11 = 2 C J (n) mod 13 = C K (n) + ∆C(n) mod 13 = 0+8 mod 13 = 8 C J (n) mod 19 = C K (n) + ∆C(n) mod 19 =11+8 mod 19 = 0 Hence, the RNS value of n = 1,859,107 (or (5,8,3,4,14,17) in RNS format) after being approximately scaled by 2717 is C J (n) = (5, 2, 8, 4, 0, 17).…”

Section: Worked Example Of Proposed Rns Scaling Algorithmmentioning

confidence: 97%

“…• They offer high-performance implementations of arithmetic-intensive applications at reduced power supply voltages, important for mobile and wearable computer and communication systems [4] • They avoid lengthy on-chip interconnects, which now represent the major constraint on the realisation of high-performance digital VLSI circuits [5] • They afford hardware-efficient complex multipliers ("QRNS multiplication") comprising two independent multiplications instead of four multiplications and two additions [1] • The component arithmetic operations in an RNS implementation can, without exception, be reduced to short adders and small look-up tables [1] All the items in the above list are applicable to custom VLSI implementations, and the last two also apply advantageously to FPGA implementations [6,7]. Recent industrial interest in RNS confirms the existence and scale of problems faced in implementing DSP algorithms in digital microelectronic fabrics at high clock rates but with low power consumption.…”

Section: Background and Motivationmentioning

confidence: 99%

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Scaling an RNS number using the core function

Burgess

16th IEEE Symposium on Computer Arithmetic, 2003. Proceedings.

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This paper introduces a method for extracting the core of a Residue Number System (RNS) number within the RNS, this affording a new method for scaling RNS numbers.Suppose an RNS comprises a set of co-prime moduli, m i , with ∏m i = M. This paper describes a method for approximately scaling such an RNS number by a subset of the moduli, ∏m j = M J ≈ √M, with the characteristic that all computations are performed using the original moduli and one other non-maintained short wordlength modulus. Background and MotivationThe Residue Number System (RNS) has great potential for accelerating arithmetic operations, achieved by breaking operands into several smaller residues and operating on the residues independently and in parallel. RNS implementations were studied extensively in the 1970's, particularly for DSP applications [1], and led to Inmos' production of an RNS 2-D convolver chip in 1989 [2]. However, wider take-up of RNS for DSP was limited because of a number of fundamental difficulties: • Conversion to binary representation from RNS is difficult (the inverse operation is simple) • Direct magnitude comparison and sign determination of RNS numbers is impossible • Square root operations are not available, and division operations, although available [3], are not practical due to their complexity These difficulties place major constraints on the possible applications of RNS arithmetic.Recently, however, DSP chips using RNS have enjoyed something of a renaissance for a variety of reasons:• They offer high-performance implementations of arithmetic-intensive applications at reduced power supply voltages, important for mobile and wearable computer and communication systems [4] • They avoid lengthy on-chip interconnects, which now represent the major constraint on the realisation of high-performance digital VLSI circuits [5] • They afford hardware-efficient complex multipliers ("QRNS multiplication") comprising two independent multiplications instead of four multiplications and two additions [1]• The component arithmetic operations in an RNS implementation can, without exception, be reduced to short adders and small look-up tables [1] All the items in the above list are applicable to custom VLSI implementations, and the last two also apply advantageously to FPGA implementations [6,7]. Recent industrial interest in RNS confirms the existence and scale of problems faced in implementing DSP algorithms in digital microelectronic fabrics at high clock rates but with low power consumption. For example, reference [8] describes an FIR filter in RNS designed by Texas Instruments because of its low-power capability, and reference [9] discusses a general-purpose DSP engine developed by Siemens that incorporates an RNS vector processor with a considerably higher data processing bandwidth than its binary counterpart.The fundamental difficulties with RNS arithmetic listed earlier have been overcome to some extent by recent innovations in RNS theory. For example, the core function has been shown to be advantageous in converting an RNS nu...

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