Technology Mapping for Reliability Enhancement in Logic Synthesis

Abstract

Abstract-Reliability enhancements are traditionally implemented through redundancies at the system level or through the use of harden-cell-designs at the circuit level. Reliability is commonly ignored during the logic synthesis step. A major reason for this is the fact that constructing a cost function to measure sensitivity to faults at the logic synthesis level is complex. The work presented in this paper addresses one important aspect of synthesis for high reliability. It focuses on the problem of mapping a technology independent circuit to a technology specific one, using gates from a given library, with Fault Sensitivity [3] as an optimization metric. We believe that the difficulty in obtaining accurate metrics of fault sensitivity at the technology independent level makes it hard to optimize at this level, thus technology dependent mapping offers a direct method to improve reliability. In this paper, we present a concept named "effective fault area" for mapping onto library gates. Along with this concept, we adopt a Markov-model based analytical method to accurately estimate fault sensitivity during mapping with a low computational overhead. Several benchmark results show that the average reliability improvement is about 20.7% at the cost of 12.1% increase in delay.