Technology-design-manufacturing co-optimization for advanced mobile SoCs

Abstract

How to maintain the Moore's Law scaling beyond the 193 immersion resolution limit is the key question semiconductor industry needs to answer in the near future. Process complexity will undoubtfully increase for 14nm node and beyond, which brings both challenges and opportunities for technology development. A vertically integrated design-technologymanufacturing co-optimization flow is desired to better address the complicated issues new process changes bring. In recent years smart mobile wireless devices have been the fastest growing consumer electronics market. Advanced mobile devices such as smartphones are complex systems with the overriding objective of providing the best userexperience value by harnessing all the technology innovations. Most critical system drivers are better system performance/power efficiency, cost effectiveness, and smaller form factors, which, in turns, drive the need of system design and solution with More-than-Moore innovations. Mobile system-on-chips (SoCs) has become the leading driver for semiconductor technology definition and manufacturing. Here we highlight how the co-optimization strategy influenced architecture, device/circuit, process technology and package, in the face of growing process cost/complexity and variability as well as design rule restrictions.

Vertical structure and innovation: A study of the SoC and smartphone industries

“…The global smartphone sales were 120 billion dollars in the last quarter of 2017 (Koetsier, 2018). The SoC is a key smartphone component that combines a mobile application processor (essentially a CPU), GPU, modem, and other chips (Yang et al, 2014). The SoC and smartphone industries provide an interesting setting to study innovation in vertically separated industries for a number of reasons.…”

Toward the 5nm technology: layout optimization and performance benchmark for logic/SRAMs using lateral and vertical GAA FETs

“…For sub-20nm technology nodes, the conventional transistor and lithography scaling purely relying on the tool and material development has hit significant difficulties [1][2][3][4][5][6][7] . Other avenues such as alternative device architecture, asymmetric pitch scaling, emerging material had to be exploited to achieve power/performance/area/cost (PPAC) scaling targets without shrinking design rules by a 0.7X factor.…”