Technological Stack for Implementation of AI as a Service based on Hardware Accelerators

Perepelitsyn, Artem; Fesenko, Herman; Kasapien, Yelyzaveta; Kharchenko, Vyacheslav

doi:10.1109/dessert58054.2022.10018615

Cited by 2 publications

(2 citation statements)

References 3 publications

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“…Цей крок дозволяє зменшити кількість задіяних бітів у представленні вузла нейронної мережі. Цей процес можна автоматизувати за допомогою інструментів розроблення [16].…”

Section: аналіз розроблення сервісів штучного інтелекту з використанн...unclassified

Забезпечення Управління Цифровими Правами Для Створення Штучного Інтелекту Як Сервісу На Основі FPGA Реалізації

Perepelitsyn

2023

aktt

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The subject of study in this article is modern FPGA technologies for creation of projects and providing them as a services, as well as solutions for ensuring digital rights management of individual instances of the system. The goal is to analyze and improve technologies for ensuring the work of licensing mechanisms and prevention of unauthorized execution of IP-cores involved in the implementation of artificial intelligence (AI) systems in FPGA. Task: to analyze the process of prototyping artificial intelligence systems and providing them as a services using FPGA; to perform an analysis of the possibility of the implementation of a rental mechanism for artificial intelligence as a service based on FPGA with licensing of individual instances of the system; to analyze the possibilities of code protection for the description of the implementation of service rental mechanisms directly in the FPGA; to perform research of possible candidate elements that allow uniqueness identification of individual instances of the system or FPGA chip; and to provide practical example of the application of mechanisms for ensuring digital rights management for creation of artificial intelligence as a service project in FPGA. According to the tasks, the following results were obtained. The analysis of technological capabilities, tools and development environments, description and programming languages for the creation of artificial intelligence systems in the form of a service with hardware implementation is performed. The components of each level of FPGA-based AI service implementation are analyzed. An analysis of possible directions for ensuring digital rights management for AI services projects in FPGA is performed. The possibility of protecting the source code of the description of hardware solutions for the possibility of distribution using the IEEE-1735 encryption standard is analyzed. The integration of the encryption standard with the development environments is discussed. A search of options and possible solutions to ensure identification of the specific instance of the project based on FPGA chip is performed. A practical study of the use of the existing solution from Accelize company for ensuring digital rights management for IP-cores of projects for FPGA is performed. Conclusions. The main contribution and scientific novelty of the obtained results is in the provided results of the research of possible candidate elements that allow the detection of differences and identification of the FPGA uniqueness for the identification of the instance of the system. The proposed method of processing of data from the implementation of physical unclonable functions (PUF) in FPGA to ensure digital rights management is a principal new approach. The given relations between the levels of implementation of AI as a service based on FPGA show the hierarchy of components when building of such system.

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Section: аналіз розроблення сервісів штучного інтелекту з використанн...unclassified

Забезпечення Управління Цифровими Правами Для Створення Штучного Інтелекту Як Сервісу На Основі FPGA Реалізації

Perepelitsyn

2023

aktt

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“…Recent approaches with Xilinx FPGAs have shifted from ad-hoc accelerators to using Xilinx's Deep-learning Processing Units (DPUs) for efficient AI service implementation. Various alternatives, including [14], [15], [16], and [17], employ DPUbased CNN models on FPGAs for hardware acceleration.…”

Section: State Of the Artmentioning

confidence: 99%

UML-Based Design Flow for Systems with Neural Networks

Suárez,

Posadas,

Fernández

2023

2023 38th Conference on Design of Circuits and Integrated Systems (DCIS)

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Artificial intelligence has demonstrated its ability to solve lots of critical tasks, but at the cost of high computational requirements. Different hardware has been proposed to provide this computational power, each one with its benefits and drawbacks. However, the exploration of the different alternatives in an easy an integrated way is still a complex task. To solve so, this paper proposes a UML-based design flow where neural networks are initially specified and then automatically generated and trained using TensorFlow. The approach also enables automatic mapping of models to CPU, GPU and FPGAs, using Xilinx's Deep Learning Processor Units (DPUs). The framework also generates the communication codes required to connect the other system components with the implementation selected. This approach addresses design-space exploration challenges, system architecture definition, and improves implementation and training processes by saving time and effort.

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Technological Stack for Implementation of AI as a Service based on Hardware Accelerators

Cited by 2 publications

References 3 publications

Забезпечення Управління Цифровими Правами Для Створення Штучного Інтелекту Як Сервісу На Основі FPGA Реалізації

Забезпечення Управління Цифровими Правами Для Створення Штучного Інтелекту Як Сервісу На Основі FPGA Реалізації

UML-Based Design Flow for Systems with Neural Networks

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