Techniques for reducing parasitic loss in switched-capacitor based DC-DC converter

Biswas, Avishek; Kar, Moumita; Mandal, Pradip

doi:10.1109/apec.2013.6520573

Cited by 6 publications

(5 citation statements)

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“…Moreover, by employing a sampled current compensation method, the estimation error is minimized. Employing an accurate model of different kind of energy converters is considered for different purposes such as loss minimization [34][35][36]. In [34], the efficiency comparison of the SiC-MOSFET and Si-IGBT-based converters is performed for DC-DC interleaved converters considering a range of switching frequency and output inductances.…”

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confidence: 99%

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Sensorless Voltage Observer for a Current-Fed High Step-Up DC-DC Converter Using Extended Kalman Filter

et al. 2020

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In high voltage applications, sensorless voltage control techniques can reduce the cost and increase the reliability of DC-DC converters. In this paper, a sensorless voltage observer for a current fed Cockcroft-Walton voltage multiplier is designed. The first step is to derive the converter model. Since any inaccuracy in the derived model can result in a discrepancy between the observed voltage and the actual output voltage, an accurate model is derived, which incorporates the influential elements. Then, two voltage observers based on the extended Kalman filter (EKF) are designed and used to estimate the output voltage, transformer magnetizing current and inductor current for two different configurations of the high step-up DC-DC converter. Experimental and simulation results of the system show the efficiency of the observers. The proposed observers represent good precision as the main parasitic parameters are considered in the converter model.

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confidence: 99%

“…In [34], the efficiency comparison of the SiC-MOSFET and Si-IGBT-based converters is performed for DC-DC interleaved converters considering a range of switching frequency and output inductances. Reference [35] is focused on a switched-capacitor version of the DC-DC buck converter. Two techniques for reducing top-plate parasitic loss are proposed.…”

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Sensorless Voltage Observer for a Current-Fed High Step-Up DC-DC Converter Using Extended Kalman Filter

et al. 2020

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“…Whereas, high voltage I/O devices were used for C 2a & C 2b , which need to support a maximum voltage of 2V in across them. For MOS capacitors soft connection of the n-well [16], [12] was adopted. As shown in Fig.9, the n-well of the MOS transistor is biased with a high resistance to the output node V out .…”

Section: Mos Implementation Of the Sub-modulementioning

confidence: 99%

“…Second and more importantly, the proposed topology offers better performance in terms of reducing bottom-plate parasitic loss, which is a significant component of the overall loss for on-chip implementation of the charge-transfer capacitors [11], [16]. On-chip capacitors offer a much higher energy density compared to their off-chip counterparts, but they suffer from having considerably more parasitic capacitance (associated with their bottom or top plate and the substrate).…”

Section: Introductionmentioning

confidence: 99%

“…On-chip capacitors offer a much higher energy density compared to their off-chip counterparts, but they suffer from having considerably more parasitic capacitance (associated with their bottom or top plate and the substrate). This parasitic can be as high as 5-10% [16] of the actual capacitance for the MOS capacitors used in this design. In SC converters, this parasitic capacitor gets charged in one phase and loses that energy by discharging in the other phase.…”

Section: Introductionmentioning

confidence: 99%

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A 28 nm FDSOI Integrated Reconfigurable Switched-Capacitor Based Step-Up DC-DC Converter With 88% Peak Efficiency

Biswas

Sinangil

Chandrakasan

2015

IEEE J. Solid-State Circuits

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Abstract-This paper presents a fully integrated, reconfigurable switched-capacitor based step-up DC-DC converter in a 28nm FDSOI process. Three reconfigurable step-up conversion ratios (5/2, 2/1, 3/2) have been implemented which can provide a wide range of output voltage from 1.2V to 2.4V with a nominal input voltage of 1V. We propose a topology for the 5/2 mode which improves the efficiency by reducing the bottomplate parasitic loss compared to a conventional series-parallel topology, while delivering the same amount of output power. Further, the proposed topology benefits from using core 1V devices for all charge-transfer switches without incurring any voltage overstress. The converter can deliver load current in the range of 10 µA to 500 µA, achieving a peak efficiency of 88%, using only on-chip MOS and MOM capacitors for a high density implementation.

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Fully Integrated Switched-Capacitor Power Converters

Jiang

Lü

et al. 2023

Analog Circuits and Signal Processing

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Techniques for reducing parasitic loss in switched-capacitor based DC-DC converter

Cited by 6 publications

References 5 publications

Sensorless Voltage Observer for a Current-Fed High Step-Up DC-DC Converter Using Extended Kalman Filter

Sensorless Voltage Observer for a Current-Fed High Step-Up DC-DC Converter Using Extended Kalman Filter

A 28 nm FDSOI Integrated Reconfigurable Switched-Capacitor Based Step-Up DC-DC Converter With 88% Peak Efficiency

Fully Integrated Switched-Capacitor Power Converters

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