Technique for Profiling the Cycling-Induced Oxide Trapped Charge in NAND Flash Memories

Abstract

NAND Flash memories have gained tremendous attention owing to the increasing demand for storage capacity. This implies that NAND cells need to scale continuously to maintain the pace of technological evolution. Even though NAND Flash memory technology has evolved from a traditional 2D concept toward a 3D structure, the traditional reliability problems related to the tunnel oxide continue to persist. In this paper, we review several recent techniques for separating the effects of the oxide charge and tunneling current flow on the endurance characteristics, particularly the transconductance reduction (ΔGm,max) statistics. A detailed analysis allows us to obtain a model based on physical measurements that captures the main features of various endurance testing procedures. The investigated phenomena and results could be useful for the development of both conventional and emerging NAND Flash memories.

High-Density Solid-State Memory Devices and Technologies

“…The fourth review paper in the Special Issue is by Chiu and Shirota [4] and summarizes a method to investigate the endurance of NAND Flash memories starting from cell transconductance. Nowadays, NAND Flash memories represent the dominant nonvolatile storage solution, and techniques allowing us to get some information about the microscopic mechanisms constraining its endurance are of utmost importance for the development of next-generation technology nodes.…”

Effects of Hydrogen on Endurance Characteristics in NAND Flash Memories

“…As the extracted Q T does not obey the power law at a large N, Eq. 1 needs to be modified as follows 20,21 ECS Advances, 2022 1 042001…”

“…In this study, we used a recently developed transconductance (G m max , ) technique, 20,21 which enabled the extraction of cyclinginduced gate oxide charge density (Q T ) to quantitatively analyze the effect of ambient hydrogen content on the endurance characteristics of NAND flash memories. The remainder of this paper is organized as follows: section 2 describes the structure of NAND flash memory devices and experiments.…”

Fabrication of a Hole‐Type Vertical Resistive‐Switching Random‐Access Array and Intercell Interference Induced by Lateral Charge Spreading

“…[ 11–13 ] These problems are fundamentally due to the quantum mechanical tunneling of electronic carriers in the V‐NAND structures. [ 14–16 ]…”

“…[11][12][13] These problems are fundamentally due to the quantum mechanical tunneling of electronic carriers in the V-NAND structures. [14][15][16] In this regard, the vertically integrated resistive switching random access memory (V-ReRAM) draws great attention because the ionic switching mechanism may suffer less from the quantum mechanical effects. Apart from the commercially available layer-by-layer stacking of the memory layers, as in the Optane memory, where the word lines (WL) and bit lines (BL) are present on the given 2D plane, such a V-ReRAM must have vertically aligned BL to minimize the Si surface area consumption by the contacts.…”