Teaching multi-core DSP implementation on EVM C6678 board

Kharin, Aleksei; Vityazev, Sergey; Vityazev, Vladimir

doi:10.23919/eusipco.2017.8081632

Cited by 5 publications

(5 citation statements)

References 14 publications

(13 reference statements)

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“…At the same time, the GTX transceivers are used to connect the SRIO hardware interface at the DSP. The high-speed full duplex serial communication of 5 GBaud per channel is realized [ 27 ].…”

Section: Hardware Designmentioning

confidence: 99%

Design and Implementation of a Real-Time Multi-Beam Sonar System Based on FPGA and DSP

Tian

Guo

Zhao

et al. 2021

Sensors

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Aiming at addressing the contradiction between the high-speed real-time positioning and multi-channel signal processing in multi-beam sonar systems, in this work we present a real-time multi-beam sonar system based on a Field Programmable Gate Array (FPGA) and Digital Signal Processing (DSP) from two perspectives, i.e., hardware implementation and software optimization. In terms of hardware, an efficient high-voltage pulse transmitting module and a multi-channel data acquisition module with time versus gain (TVG) compensation with characteristics such as low noise and high phase amplitude consistency, are proposed. In terms of algorithms, we study three beamforming methods, namely delay-and-sum (D&S), direct-method (DM) and Chirp Zeta Transform (CZT). We compare the computational efficiency of DM and CZT in the digital domain. In terms of software, according to the transmission bandwidth of the Gigabit Ethernet and a serial rapid IO (SRIO) interface, the data transmission paths of the acquired data and the beam pattern between the FPGA, the DSP, and a personal computer (PC) are planned. A master-slave multi-core pipelined signal processing architecture is designed based on DSP, which enhances the data throughput of the signal processor by seven times as compared with that of the single-core operation. The experimental results reveal that the sound source level of the transmitting module is around 190.25 dB, the transmitting beam width is 64° × 64°, the background noise of the acquisition module is less than 4 μVrms, the amplitude consistency error of each channel is less than −6.55 dB, and the phase consistency error is less than 0.2°. It is noteworthy that the beam number of the sonar system is 90 × 90, the scanning angle interval is 0.33°, the working distance ranges from 5 m to 40 m, and the maximum distance resolution is 0.384 m. In the positioning experiment performed in this work; the 3-D real-time position of the baffle placed in the detection sector is realized. Please note that the maximum deviation of azimuth is 2°, the maximum deviation of elevation is 2.3°, and the maximum distance deviation is 0.379 m.

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Section: Hardware Designmentioning

confidence: 99%

Design and Implementation of a Real-Time Multi-Beam Sonar System Based on FPGA and DSP

Tian

Guo

Zhao

et al. 2021

Sensors

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“…Should a computational core experience anomalies and fail to complete the handshake communication, it will not advance to the subsequent phases, prompting the system to restart the process. During the computation process of the computational cores, the previously mentioned DNUM [8] is utilized to limit the operation of core 0, which is in a loop continuously monitoring the result flags set by the computational cores. However, should the computational cores encounter any anomalies, core 0 risks entering an infinite loop.…”

Section: Improved Multi-core Master-slave Topology Architecturementioning

confidence: 99%

“…Figure 6. Improved multi-core architecture.During the computation process of the computational cores, the previously mentioned DNUM[8] is utilized to limit the operation of core 0, which is in a loop continuously monitoring the result flags set by the computational cores. However, should the computational cores encounter any anomalies, core 0 risks entering an infinite loop.…”

mentioning

confidence: 99%

Software architecture and implementation based on multi-core digital signal processors

Yuan,

Meng

2024

J. Phys.: Conf. Ser.

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Embedded detection systems are a critical research topic in intelligent monitoring equipment. In response to the current challenges in balancing real-time performance, accuracy, and stability in embedded hardware detection systems, this paper proposes a software architecture system based on multi-core digital signal processing (DSP), incorporating the image detection Canny algorithm into this system. Initially, the paper discusses the selection criteria for multi-core DSPs and then introduces a multi-core self-check function that can effectively ensure system stability. It also proposes a multi-core communication handshake protocol that significantly enhances the system’s real-time performance. Furthermore, an improved multi-core master-slave architecture is presented, which includes the addition of a timer to the conventional architecture, providing a temporal guarantee for system operation. Finally, the Canny algorithm is selected and applied to this software architecture, with parallel acceleration processing applied to parts of the algorithm. Operational tests have demonstrated that the system maintains stable internal data flow, with its detection accuracy and speed meeting the set requirements.

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“…The experimental platform consists of one development board EVM6678 as shown in Figure 4, which integrates one C6678 DSP and 512MB of DDR3 memory [25,26]. The multi-core C6678 DSP provided by TI is a high-performance computing and low power system.…”

Section: C6678 Dsp Overviewmentioning

confidence: 99%

Parallel implementation of pulse compression method on a multi-core digital signal processor

Klilou

2020

IJECE

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Pulse compression algorithm is widely used in radar applications. It requires a huge processing power in order to be executed in real time. Therefore, its processing must be distributed along multiple processing units. The present paper proposes a real time platform based on the multi-core digital signal processor (DSP) C6678 from Texas Instruments (TI). The objective of this paper is the optimization of the parallel implementation of pulse compression algorithm over the eight cores of the C6678 DSP. Two parallelization approaches were implemented. The first approach is based on the open multi processing (OpenMP) programming interface, which is a software interface that helps to execute different sections of a program on a multi core processor. The second approach is an optimized method that we have proposed in order to distribute the processing and to synchronize the eight cores of the C6678 DSP. The proposed method gives the best performance. Indeed, a parallel efficiency of 94% was obtained when the eight cores were activated.

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Teaching multi-core DSP implementation on EVM C6678 board

Cited by 5 publications

References 14 publications

Design and Implementation of a Real-Time Multi-Beam Sonar System Based on FPGA and DSP

Design and Implementation of a Real-Time Multi-Beam Sonar System Based on FPGA and DSP

Software architecture and implementation based on multi-core digital signal processors

Parallel implementation of pulse compression method on a multi-core digital signal processor

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