TDDB chip reliability in copper interconnects

Abstract

Backend time dependent dielectric breakdown (TDDB) degrades the reliability of circuits with copper interconnects. We use test data to develop a methodology to evaluate chip lifetimes, because of backend TDDB, from layout statistics. We identify features in a layout that are critical to backend reliability, present a model to incorporate those features in determining chip lifetimes, and study the effect of different layout optimizations on chip lifetime.

Degradation in TDDB of Cu/low-k test structures due to field interaction between adjacent metal lines

“…Small area test structures were originally designed by Tan et al for the purpose of studying failure analysis of low-k dielectric [1]. This structure also mimics some shape and area that may be found in the real test structures, but are not represented by the conventional comb structures often used for reliability studies of dielectric breakdowns [2].…”