TCAD study of latch-up sensitivity to wafer thinning below 500 nm

Hiblot, Gaspard; Serbulova, Kateryna; Hellings, Geert; Chen, Shih-Hung

doi:10.1109/cas52836.2021.9604133

Cited by 2 publications

(1 citation statement)

References 18 publications

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“…From a circuit-level hardness perspective, the devices will exit the SEL when the latch-up currents or latch-up voltages fall below the holding currents or voltages. To improve the SEL immunity of CMOS devices, three dominant research directions are proposed, respectively process-level hardness, layout-level hardness, and circuit-level hardness [18][19][20]. Both process-level and layout-level designs enable the devices to be protected from SEL, while neither is applicable to commercial devices that have already been designed for production [21][22][23].…”

Section: Introductionmentioning

confidence: 99%

Study of Single Event Latch-Up Hardness for CMOS Devices with a Resistor in Front of DC-DC Converter

Xin

Zhu

et al. 2023

Electronics

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Bulk silicon Complementary Metal Oxide Semiconductor (CMOS) devices have distinct single event latch-up (SEL) problems in aerospace. Therefore, it is essential that CMOS devices are designed with appropriate circuit-level methods. Traditional resistor hardness satisfies the current aerospace trend of low cost, high performance, and miniaturization. Therefore conventional resistor hardness is often applied in circuit-level designs due to the reduction of latch-up current. In circuits containing a DC-DC buck converter, the resistor is connected to the back of the converter in the traditional method. However, the traditional method is unable to take devices out of the latch-up owing to the small resistance range. To solve this problem, the paper proposes an improved design for the resistor in front of the DC-DC buck converter. The proposed method enables the devices to exit the latch-up by increasing the resistance range according to the input characteristic of the DC-DC buck converter. The paper quantifies the range of the resistor through the parametric model containing the resistor and the DC-DC buck converter. Two CMOS devices are chosen for pulsed laser experiments, verifying that the proposed method increases the resistance ranges by 300% to 400% compared to the conventional method. It is also demonstrated that the proposed method exits the devices from latch-up within the resistor ranges. That is, the resistance ranges of 34 Ω~41 Ω and 51 Ω~56 Ω reduce the latch-up currents of the devices to below holding currents of 72.1 mA and 24.2 mA, respectively.

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