TCAD simulation of planar single-gate Si tunnel FET with average subthreshold swing less than 60 mV/dec for 0.3 V operation

Kukita, Kentaro; Uechi, T.; Shimokawa, J.; Goto, Masahiro; Yokota, Yoshiharu; Kawanaka, S.; Tanamoto, Tetsufumi; Koyama, Masahiro; Tanimoto, Hiroki; Takagi, Shigetaka

doi:10.7567/ssdm.2017.ps-3-14

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“…In the previous our work, 29) it was also shown that TFET without pocket can be achieved the good characteristics as same as TFET with pocket doping. However, these reasons and detailed backgrounds were not mentioned.…”

Section: Introductionmentioning

confidence: 52%

Simulation of planar single-gate Si tunnel FET with average subthreshold swing of less than 60 mV/decade for 0.3 V operation

Kukita

Uechi

Shimokawa

et al. 2018

Jpn. J. Appl. Phys.

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Planar single-gate (SG) silicon (Si) tunnel field effect transistors (TFETs) are attracting interest for ultra-low voltage operation and CMOS applications. For the achievement of subthreshold swing (S.S.) less than thermal limit of Si MOSFETs (S.S. = 60 mV/decade at 300 K), previous studies have proposed the formation of a pocket region, which needs very difficult implantation process. In this work, a planar SG Si TFET without pocket was proposed by using the technology computer-aided design (TCAD) simulations. An average S.S. of less than 60 mV/decade for 0.3 V (= V gs = V ds ) operation was obtained. It is found that both low average S.S. (= 27.8 mV/decade) and high on-current I on (= 3.8 µA/µm) are achieved without pocket doping by scaling the equivalent oxide thickness (EOT) and increasing the gate-to-source overlap length L ov .

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Section: Introductionmentioning

confidence: 52%