TCAD Analysis of the Four-Terminal Poly-Si TFTs on Suppression Mechanisms of the DC and AC Hot-Carrier Degradation

Gao, Ting; Wang, Mingxiang; Wang, Huaisheng; Zhang, Dongli

doi:10.1109/jeds.2019.2916619

Cited by 10 publications

(5 citation statements)

References 16 publications

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“…Acceptor-like trap states play an important role in the dynamic degradation of n-type TFTs under bipolar gate bias stress [28], so the degradation of a pristine TFT and one TFT underwent NBIS after the same bipolar gate pulse stress is compared, where the pulse valley voltage is 20 V and the pulse peak voltage is 20 V, the pulse rising and falling time are 0.1 s and the pulse duty ratio is 50%. As shown in Fig.…”

Section: Resultsmentioning

confidence: 99%

Increased Threshold Voltage of Amorphous InGaZnO Thin-Film Transistors After Negative Bias Illumination Stress

Hong,

Zhang,

Zhang

et al. 2024

IEEE J. Electron Devices Soc.

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Degradation phenomena featured with positive shift of the on-state transfer curve are reported for the amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) under negative bias illumination stress (NBIS). Such a positive shift is absent when the gate bias or the illumination is independently applied. With the assistance of TCAD simulation, the positive shift of the transfer curve is attributed to the generation of acceptor-like trap states, which is proposed to be due to oxygen interstitials produced as a consequence of electron generation by the illumination, acceleration under the effect of negative gate bias, and breaking weakly bonded oxygen. The proposed degradation mechanism is consistent with the low frequency noise characteristics and the degradation behavior under bipolar gate bias stress of the TFTs after NBIS. The whole degradation phenomena for the a-IGZO TFT under the NBIS are then consistently explained.

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Section: Resultsmentioning

confidence: 99%

Increased Threshold Voltage of Amorphous InGaZnO Thin-Film Transistors After Negative Bias Illumination Stress

Hong,

Zhang,

Zhang

et al. 2024

IEEE J. Electron Devices Soc.

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“…For simplicity, moreover, the polycrystalline nature of the silicon channel that results from the manufacturing process with the current technology [20], [21] was represented following [22], where the nonuniform polysilicon with a granular structure is treated as a uniform material with spatially uniform bulk traps. A large number of papers confirmed the validity of such an approach, reporting trap energy distributions with a double-exponential shape in the energy gap [23], [24], [25], [26], [27], [28], [29], [30], [31], i.e.,…”

Section: Table I Structure Parametersmentioning

confidence: 89%

Time Dynamics of the Down-Coupling Phenomenon in 3-D NAND Strings

Giulianini

Malavena

Compagnoni

et al. 2022

IEEE Trans. Electron Devices

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We present a detailed analysis of the time dynamics of the down-coupling phenomenon (DCP) in 3-D NAND Flash memory strings. The transient time dynamics of the channel potential following the wordline (WL) bias transition from the pass voltage to zero is studied via numerical simulation, highlighting the existence of three temporal regimes controlled by different physical processes: electron emission from traps, hole injection from the string edges followed by capture, and propagation along the string. The impact of these processes is separately studied, followed by an analysis of the dependence of the DCP recovery time on architectural parameters. Results highlight the relevant physics and can be used as a design guideline for NAND strings with reduced sensitivity to the DCP. Index Terms-3-D NAND Flash memories, down-coupling phenomenon (DCP), gate-induced drain leakage (GIDL) current, macaroni MOSFET, self-boosting effect. I. INTRODUCTIONT HE transition from planar to 3-D NAND Flash memories has allowed the pursuit of astonishing results in terms of density and cost [1], stacking more than 170 memory layers and overcoming the 10-Gb/mm 2 density figure [2], [3]. To continue along this path, however, an ever-increasing number of challenges from the process, design, and system viewpoints must be overcome [4], on top of which we must also account for reliability. From this standpoint, the peculiar architecture of 3-D NAND has brought to the forefront new concerns that add to the well-known problems inherited from planar arrays [5]. Examples of such new issues include phenomena related to the polycrystalline nature of the conduction channel [6], [7], [8],[9], [10], [11] and issues connected to floating-body effects in the vertical string channels.The down-coupling phenomenon (DCP) is one of the latter. Reported for the first time in 2016 [12], it describes the sudden drop in the channel potential V ch of the string that can result following a wordline (WL) step from the pass Manuscript

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“…Recent simulation studies of poly-Si TFTs were reported in [6,[29][30][31]. A double-gate TFT was investigated in [6], where the poly-Si channel layer was controlled by a top gate and a bottom gate.…”

Section: Introductionmentioning

confidence: 99%

“…However, influences of defects on the TFT performance were not studied. Gao et al used TCAD simulation to explore the mechanism of the hot-carrier degradation for a four-terminal poly-Si TFT [29]. Investigation of the defect density variation caused by a passivation process of a singlegate poly-Si TFT was proposed in [30].…”

Section: Introductionmentioning

confidence: 99%

“…A dramatic reduction in the hole concentration at the grain boundary protrusion site explains the decreased mobility. Above literature survey indicates that the TCAD simulation is important for investigation of poly-Si TFTs, and usually uniform bulk defects in the channel layer are considered when performaing the TCAD analysis [6,29,30]. Meanwhile, simulation study of dual-gate TFTs is seldom reported.…”

Section: Introductionmentioning

confidence: 99%

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Performance dependence of self-aligned dual-gate poly-Si TFTs on localized defective regions

Hsu¹,

Li²,

Chen³

et al. 2020

Semicond. Sci. Technol.

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This study investigates effects of localized defect regions on electrical characteristics of self-aligned dual-gate poly-Si thin-film transistors (TFTs). The thickness of the poly-Si channel layer ranges from 20 nm to 140 nm. The threshold voltage, subthreshold swing, and mobility are found to be sensitive to the defect position. The localized defects in the left channel (source side) exhibit a significant impact while those in the right channel (drain side) show a lower influence on the TFT performance. In addition, the performance variation caused by the localized defects in the right channel is highly sensitive to the magnitude of the applied drain bias. A higher drain bias can observably reduce the performance degradation. Effects of multiple defect regions on the electrical behavior of the TFTs are also explored. We found that the upper width of the defect regions dominates the TFT performance deterioration. The hole transport, hole concentration distributions, and current flowlines are analyzed to study the physical mechanisms.

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TCAD Analysis of the Four-Terminal Poly-Si TFTs on Suppression Mechanisms of the DC and AC Hot-Carrier Degradation

Cited by 10 publications

References 16 publications

Increased Threshold Voltage of Amorphous InGaZnO Thin-Film Transistors After Negative Bias Illumination Stress

Increased Threshold Voltage of Amorphous InGaZnO Thin-Film Transistors After Negative Bias Illumination Stress

Time Dynamics of the Down-Coupling Phenomenon in 3-D NAND Strings

Performance dependence of self-aligned dual-gate poly-Si TFTs on localized defective regions

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