Task Scheduling Techniques for Asymmetric Multi-Core Systems

Abstract

Abstract-As performance and energy efficiency have become the main challenges for next-generation high-performance computing, asymmetric multi-core architectures can provide solutions to tackle these issues. Parallel programming models need to be able to suit the needs of such systems and keep on increasing the application's portability and efficiency. This paper proposes two task scheduling approaches that target asymmetric systems. These dynamic scheduling policies reduce total execution time either by detecting the longest or the critical path of the dynamic task dependency graph of the application, or by finding the earliest executor of a task. They use dynamic scheduling and information discoverable during execution, fact that makes them implementable and functional without the need of off-line profiling. In our evaluation we compare these scheduling approaches with two existing state-of the art heterogeneous schedulers and we track their improvement over a FIFO baseline scheduler. We show that the heterogeneous schedulers improve the baseline by up to 1.45× in a real 8-core asymmetric system and up to 2.1× in a simulated 32-core asymmetric chip.

A Hardware Runtime for Task-Based Programming Models

“…The critical tasks considered are the ones in the task chain with the highest number of tasks. The criticalpath scheduler (CPATH) [8], [9] extended the consideration of task execution time for critical tasks. The version scheduler [10] described a scheduling policy to schedule tasks to either processors or GPUs in the system.…”

“…For homogeneous multicores, task dependence analysis is the most critical function [5], [6], [7]. For heterogeneous architectures, the task scheduling cost is also very high due to the load balance challenge caused by the execution time difference, the necessary data movements and synchronization between different memories [8], [9], [10]. Previous works of hardware task dependence management have showed great scalability and performance improvement over their software-only alternatives [4], [11], [12], [13].…”

Evaluating Scientific Workflow Execution on an Asymmetric Multicore Processor

“…Problem Description: The problem of task scheduling onto heterogeneous HPC systems has been extensively studied [2,[10][11][12]14,15], with several works focusing on multicore processors [1,3,8,10,16]. Some of the algorithms focus on optimizing application performance and execution time [10,12], while other works also consider energy and power optimization [1,8].…”

“…Some of the algorithms focus on optimizing application performance and execution time [10,12], while other works also consider energy and power optimization [1,8]. As heterogeneous multicore processing platforms integrating different types of processing cores are now used as a promising solution towards achieving different performance and power goals, there has been research on policies which aim to determine which types of cores are more appropriate for the scheduling of the applications or their parts [3,10,13]. For example, power-efficient cores may be used for the execution of memory-bound or non-critical jobs while fast cores may be more suitable for CPU-bound or critical jobs [3,13].…”

An Improved Scheduling Algorithm for Data Transmission in Ultrasonic Phased Arrays with Multi-Group Ultrasonic Sensors

“…Unfortunately, the process of the reallocation will make the time slice resources more fragmented, and increase the complexity of the scheduling algorithm. Multiple examples of implementation for the scheduling algorithm are available in the open literatures [ 16 , 17 , 18 , 19 , 20 , 21 , 22 , 23 ]. Srinivasan et al designed a self-configuring scheduling protocol for ultrasonic sensor systems by using an algorithm of the timeslot allocation, which simplified the deployment of the present detection system [ 16 ].…”