Task scheduling and voltage selection for energy minimization

Zhang, Yumin; Hu, Xiaobo Sharon; Chen, Danny Z.

doi:10.1145/513918.513966

Cited by 181 publications

(127 citation statements)

References 15 publications

(14 reference statements)

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“…For example, Zhang et al [7] formulated the task scheduling problem with voltage selection together as an integer linear programming (ILP) problem. Shin and Kim [8] and Luo and Jha [13] proposed the conditionaware DVS tasking scheduling algorithm, which can handle more complicated conditional task graphs.…”

Section: Related Workmentioning

confidence: 99%

Temperature-Aware Task Allocation and Scheduling for Embedded Multiprocessor Systems-on-Chip (MPSoC) Design

Xie

Hung

2006

J VLSI Sign Process Syst Sign Image Video Technol

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Temperature affects not only the performance but also the power, reliability, and cost of the embedded system. This paper proposes a temperature-aware task allocation and scheduling algorithm for MPSoC embedded systems. Thermal-aware heuristics are developed, and a temperature-aware floorplanning tool is used to reduce the peak temperature and achieve a thermally even distribution while meeting real time constraints. The paper investigates both power-aware and thermal-aware approaches to the task allocation and scheduling. The experimental results show that the thermal-aware approach outperforms the power-aware schemes in terms of maximal and average temperature reductions. To the best of our knowledge, this is the first MPSoC task allocation and scheduling algorithm that takes temperature into consideration.

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Section: Related Workmentioning

confidence: 99%

Temperature-Aware Task Allocation and Scheduling for Embedded Multiprocessor Systems-on-Chip (MPSoC) Design

Xie

Hung

2006

J VLSI Sign Process Syst Sign Image Video Technol

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“…For DVS processors, a higher supply voltage, generally, leads to not only a higher execution speed/frequency but also higher power consumption. As a result, DVS scheduling algorithms, e.g., Yao et al (1995), Zhang et al (2002), Aydin et al (2001), tend to execute events as slowly as possible, without any violation of timing constraints. On the other hand, dynamic power management (DPM) with clock gating or voltage gating can be applied to change the device power mode, e.g., to a sleep mode, to consume less (static/leakage) power.…”

Section: Related Workmentioning

confidence: 99%

Applying real-time interface and calculus for dynamic power management in hard real-time systems

et al. 2011

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Power dissipation has been an important design issue for a wide range of computer systems in the past decades. Dynamic power consumption due to signal switching activities and static power consumption due to leakage current are the two major sources of power consumption in a CMOS circuit. As CMOS technology advances towards deep sub-micron domain, static power dissipation is comparable to or even more than dynamic power dissipation. This article explores how to apply dynamic power management to reduce static power for hard real-time systems. We propose online algorithms that adaptively control the power mode of a system, procrastinating the processing of arrived events as late as possible. To cope with multiple event streams with different characteristics, we provide solutions for preemptive earliest-deadline-first and fixed-priority scheduling policies. By adopting a worstcase interval-based abstraction, our approach can not only tackle arbitrary event ar-164 Real-Time Syst (2011) 47: 163-193 rivals, e.g., with burstiness, but also guarantee hard real-time requirements with respect to both timing and backlog constraints. We also present extensive simulation results to demonstrate the effectiveness of our approaches.

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“…Zhang, Hu and Chen [27] proposed a two phase process for energy managed scheduling of fixed task graphs on multiprocessors. In the first phase, they use a priority based task ordering and scheduling.…”

Section: Scheduling To Lower Energy Consumptionmentioning

confidence: 99%

Energy aware DAG scheduling on heterogeneous systems

Baskiyar

Abdel-Kader

2010

Cluster Comput

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We address the problem of scheduling directed a-cyclic task graph (DAG) on a heterogeneous distributed processor system with the twin objectives of minimizing finish time and energy consumption. Previous scheduling heuristics have assigned DAGs to processors to minimize overall run-time of the application. But applications on embedded systems, such as high performance DSP in image processing, multimedia, and wireless security, need schedules which use low energy too.We develop a new scheduling algorithm called Energy Aware DAG Scheduling (EADAGS) on heterogeneous processors that can run on discrete operating voltages. Such processors can scale down their voltages and slow down to reduce energy whenever they idle due to task dependencies. EADAGS combines dynamic voltage scaling (DVS) with Decisive Path Scheduling (DPS) to achieve the twin objectives. Using simulations we show average energy consumption reduction over DPS by 40%. Energy savings increased with increasing number of nodes or increasing Communication to Computation Ratios and decreased with increasing parallelism or increasing number of available processors. These results were based on a software simulation study over a large set of randomly generated graphs as well as graphs for real-world problems with various characteristics.

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Task scheduling and voltage selection for energy minimization

Cited by 181 publications

References 15 publications

Temperature-Aware Task Allocation and Scheduling for Embedded Multiprocessor Systems-on-Chip (MPSoC) Design

Temperature-Aware Task Allocation and Scheduling for Embedded Multiprocessor Systems-on-Chip (MPSoC) Design

Applying real-time interface and calculus for dynamic power management in hard real-time systems

Energy aware DAG scheduling on heterogeneous systems

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