Task dependency aware IP core for dynamic scheduling in MPSoC environment

Abstract

This paper deals with Intellectual Property (IP) core design for dynamic task scheduling to support Out-of-Order (OoO) execution in Multiprocessor System-on-Chip (MPSoC) environment. MPSoC is one of the most promising future processor architecture. But such systems have to face challenges in the context of OoO execution during dynamic scheduling due to data dependencies like Read-after-Write (RAW), Write-after-Write (WAW) and Write-after-Read (WAR). Due to these dependencies stalling problem occur during OoO execution. In order to solve this stalling problem and achieve task level parallelism (TLP), Scoreboarding algorithm with register renaming technique is designed. As these dependencies impose challenging constraints on the direct use of techniques like OoO execution, register renaming and dynamic scheduling, a synthesizable IP core is designed. The simulation results show that the design can analyze all the task dependencies during runtime and resolves them at TLP. This algorithm is able to resolve 100% RAW, WAW and WAR hazards which are not solvable at instruction level parallelism (ILP).

Energy Aware Parallel Scheduling Techniques for Network-on-Chip Based Systems

“…In terms of modalities and implementation, majority of the strategies discussed in the related work are identical. For example, the work in [1], [20], [31] [32,33], [34], [24], [28] and [30] are based on the sequential mapping approach. The sequential schemes have high computational complexity and consume significant amount of time and resources, especially when dealing with large workflows, such as brain imaging workflows, health care data analysis, and Pegasus workflow that tackle thousands of tasks [35][36][37].…”