Task-based parallel H.264 video encoding for explicit communication architectures

Alvanos, Michail; Tzenakis, George; Nikolopoulos, Dimitrios S.; Bilas, Angelos

doi:10.1109/samos.2011.6045464

Cited by 8 publications

(8 citation statements)

References 16 publications

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“…The parallelization of the x264 encoder is performed by assigning different frames to different threads, enabling coarse-grain frame based parallelization [47]. Figure 13 shows the speedup results of ARDG IP and x264 with respect to the number of parallel threads.…”

Section: Performance Evaluation With the H264/avc Encodermentioning

confidence: 99%

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Exploiting Thread-Level Parallelism on HEVC by Employing a Reference Dependency Graph

Kim

et al. 2016

IEEE Trans. Circuits Syst. Video Technol.

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This paper presents an optimized parallel algorithm for the next-generation video codec HEVC. The proposed method provides maximized parallel scalability by exploiting two levels of parallelism: frame-level and tasklevel. Frame-level parallelism is exploited by using a graph that efficiently provides a parallel coding order of the frames with complex reference dependencies. The proposed Reference Dependency Graph is generated at runtime by a novel construction algorithm that dynamically analyzes the configuration of the HEVC codec.Task-level parallelism is exploited to provide further scalability to frame-level parallelization. A pipelined execution is allowed for independent tasks, which are defined by dividing and categorizing a single coding process into multiple types of tasks. The proposed parallel encoder and decoder do not suffer from loss in coding efficiency because neither constraints nor modification in coding options are required. The proposed parallel methods result in an average encoding speedup of 1.75 and the aggressive method that exploits additional frame-level parallelism achieved 6.52 speedup using eight physical cores.Abstract-This paper presents an optimized parallel algorithm for the next-generation video codec HEVC. The proposed method provides maximized parallel scalability by exploiting two levels of parallelism: frame-level and task-level. Frame-level parallelism is exploited by using a graph that efficiently provides a parallel coding order of the frames with complex reference dependencies. The proposed Reference Dependency Graph is generated at runtime by a novel construction algorithm that dynamically analyzes the configuration of the HEVC codec. Tasklevel parallelism is exploited to provide further scalability to frame-level parallelization. A pipelined execution is allowed for independent tasks, which are defined by dividing and categorizing a single coding process into multiple types of tasks. The proposed parallel encoder and decoder do not suffer from loss in coding efficiency because neither constraints nor modification in coding options are required. The proposed parallel methods result in an average encoding speedup of 1.75 and the aggressive method that exploits additional frame-level parallelism achieved 6.52 speedup using eight physical cores.

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Section: Performance Evaluation With the H264/avc Encodermentioning

confidence: 99%

“…In other words, a thread falls into a waiting state when the encoding of the referring part of the reference frame is not yet completed [47]. In consequence, the waiting state may propagate through multiple threads, further complicating the synchronization overhead.…”

Section: Performance Evaluation With the H264/avc Encodermentioning

confidence: 99%

Exploiting Thread-Level Parallelism on HEVC by Employing a Reference Dependency Graph

Kim

et al. 2016

IEEE Trans. Circuits Syst. Video Technol.

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“…It uses previously decoded frames to reconstruct current frame. For more details of H.264 see [3][4][5].…”

Section: Encode and Decodementioning

confidence: 99%

Parallelization of video compressing with FFmpeg and OpenMP in supercomputing environment

Kelemen

Békési

Galambos

et al. 2015

Proceedings of the 9th International Conference on Applied Informatics, Volume 1

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The application of data compression has an increasing importance in the data transfer on digital networks. In the case of real time applications the limitations of these techniques are the compression/decompression time and the bandwidth of the network. In multicore environment the compression/decompression time is reducible with parallelism. OpenMP (Open Multi-Processing) is a compiler extension that enables to add parallelism into existing source code [1, 2]. It is available in most FORTRAN and C/C++ compilers. H.264 [3] is currently one of the most commonly used video compression format. Freeware version of H.264 is available in FFmpeg library [4]. This paper describes the use of OpenMP and H.264 library in multicore environment.

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“…The encoder could encode CIF resolution video sequences at a frame rate of 30 fps. For cell processor, Alvanos et al [9] presented a way to implement fine grained task level parallelism of encoder. The runtime Tagged Procedure Calls (TPC) and a task-based programming model are used to parallelize the encoder.…”

Section: Literature Reviewmentioning

confidence: 99%

“…Alvanos et al [9] divide the MB encoding process in three phases including analyzing and encoding, entropy encoding, and deblocking. After that, each phase is executed as a separate task.…”

Section: Comparison Of the Proposed Architecture With Recentmentioning

confidence: 99%

A Hybrid Scheme Based on Pipelining and Multitasking in Mobile Application Processors for Advanced Video Coding

Asif

Taj

Ziauddin

et al. 2015

Scientific Programming

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One of the key requirements for mobile devices is to provide high-performance computing at lower power consumption. The processors used in these devices provide specific hardware resources to handle computationally intensive video processing and interactive graphical applications. Moreover, processors designed for low-power applications may introduce limitations on the availability and usage of resources, which present additional challenges to the system designers. Owing to the specific design of the JZ47x series of mobile application processors, a hybrid software-hardware implementation scheme for H.264/AVC encoder is proposed in this work. The proposed scheme distributes the encoding tasks among hardware and software modules. A series of optimization techniques are developed to speed up the memory access and data transferring among memories. Moreover, an efficient data reusage design is proposed for the deblock filter video processing unit to reduce the memory accesses. Furthermore, fine grained macroblock (MB) level parallelism is effectively exploited and a pipelined approach is proposed for efficient utilization of hardware processing cores. Finally, based on parallelism in the proposed design, encoding tasks are distributed between two processing cores. Experiments show that the hybrid encoder is 12 times faster than a highly optimized sequential encoder due to proposed techniques.

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Task-based parallel H.264 video encoding for explicit communication architectures

Cited by 8 publications

References 16 publications

Exploiting Thread-Level Parallelism on HEVC by Employing a Reference Dependency Graph

Exploiting Thread-Level Parallelism on HEVC by Employing a Reference Dependency Graph

Parallelization of video compressing with FFmpeg and OpenMP in supercomputing environment

A Hybrid Scheme Based on Pipelining and Multitasking in Mobile Application Processors for Advanced Video Coding

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